Datasheet

Figure 41: SPI timing diagram - master mode
(1)
ai14136b
SCK output
CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
M SB OUT
BIT6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BIT1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
I
2
C interface characteristics10.3.9
Table 46: I
2
C characteristics
Unit
Fast mode I
2
C
(1)
Standard mode I
2
C
ParameterSymbol
Max
(2)
Min
(2)
Max
(2)
Min
(2)
μs
-1.3-4.7SCL clock low timet
w(SCLL)
-0.6-4.0SCL clock high timet
w(SCLH)
ns
-100-250SDA setup timet
su(SDA)
900
(3)
0
(4)
-0
(3)
SDA data hold timet
h(SDA)
300-1000-SDA and SCL rise time
t
r(SDA)
t
r(SCL)
300-300-SDA and SCL fall time
t
f(SDA)
t
f(SCL)
μs
-0.6-4.0START condition hold timet
h(STA)
-0.6-4.7Repeated START condition setup timet
su(STA)
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STM8S903K3 STM8S903F3Electrical characteristics