Datasheet

Unit
Max
(1)
TypConditionsParameterSymbol
-48
(6)
HSI
(after
Flash in operating
mode
(5)
MVR voltage
regulator
off
(4)
Wakeup time active
halt mode to run
mode
(3)
wakeup)
-50
(6)
HSI
(after
Flash in
power-down
MVR voltage
regulator
Wakeup time active
halt mode to run
wakeup)mode
(5)
off
(4)
mode
(3)
-52Flash in operating mode
(5)
Wakeup time from
halt mode to run
t
WU(H)
-54Flash in power-down mode
(5)
mode
(3)
(1)
Data guaranteed by design, not tested in production.
(2)
t
WU(WFI)
= 2 x 1/f
master
+ 6 x 1/f
CPU.
(3)
Measured from interrupt event to interrupt vector fetch.
(4)
Configured by the REGAH bit in the CLK_ICKR register.
(5)
Configured by the AHALT bit in the FLASH_CR1 register.
(6)
Plus 1 LSI clock depending on synchronization.
Total current consumption and timing in forced reset state10.3.2.6
Table 32: Total current consumption and timing in forced reset state
Unit
Max
(1)
TypConditionsParameterSymbol
μA
-400V
DD
= 5 VSupply current in reset
state
(2)
I
DD(R)
-300V
DD
= 3.3 V
μs150-
Reset pin release to
vector fetch
t
RESETBL
(1)
Data guaranteed by design, not tested in production.
(2)
Characterized with all I/Os tied to V
SS
.
Current consumption of on-chip peripherals10.3.2.7
Subject to general operating conditions for V
DD
and T
A
.
61/116DocID15590 Rev 8
Electrical characteristicsSTM8S903K3 STM8S903F3