Datasheet

Reset

status

0xFFADC high threshold register lowADC_HTRL

0x00 5409

0x00ADC low threshold register highADC_LTRH

0x00 540A

0x00ADC low threshold register lowADC_LTRL

0x00 540B

0x00ADC analog watchdog status register highADC_AWSRH

0x00 540C

0x00ADC analog watchdog status register lowADC_AWSRL

0x00 540D

0x00ADC analog watchdog control register highADC _AWCRH

0x00 540E

0x00ADC analog watchdog control register lowADC_AWCRL

0x00 540F

Reserved area (1008 bytes)

0x00 5410 to

0x00 57FF

(1)

Depends on the previous reset source.

(2)

Write only register.

CPU/SWIM/debug module/interrupt controller registers6.2.3

Table 9: CPU/SWIM/debug module/interrupt controller registers

Reset statusRegister nameRegister labelBlockAddress

0x00AccumulatorA

CPU

(1)

0x00 7F00

0x00Program counter extendedPCE0x00 7F01

0x00Program counter highPCH0x00 7F02

0x00Program counter lowPCL0x00 7F03

0x00X index register highXH0x00 7F04

0x00X index register lowXL0x00 7F05

0x00Y index register highYH0x00 7F06

0x00Y index register lowYL0x00 7F07

0x03Stack pointer highSPH0x00 7F08

DocID15590 Rev 838/116

STM8S903K3 STM8S903F3Memory and register map