Datasheet

•
Transmission error detection with interrupt generation
•
Parity control
Synchronous communication
•
Full duplex synchronous transfers
•
SPI master operation
•
8-bit data communication
•
Maximum speed: 1 Mbit/s at 16 MHz (f
CPU
/16)
LIN master mode
•
Emission: Generates 13-bit synch break frame
•
Reception: Detects 11-bit break frame
SPI4.14.2
•
Maximum speed: 8 Mbit/s (f
MASTER
/2) both for master and slave
•
Full duplex synchronous transfers
•
Simplex synchronous transfers on two lines with a possible bidirectional data line
•
Master or slave operation - selectable by hardware or software
•
CRC calculation
•
1 byte Tx and Rx buffer
•
Slave/master selection input pin
I²C4.14.3
•
I²C master features:
-
Clock generation
-
Start and stop generation
•
I²C slave features:
-
Programmable I2C address detection
-
Stop bit detection
•
Generation and detection of 7-bit/10-bit addressing and general call
•
Supports different communication speeds:
-
Standard speed (up to 100 kHz)
-
Fast speed (up to 400 kHz)
DocID15590 Rev 818/116
STM8S903K3 STM8S903F3Product overview