Datasheet

[ ] 0: IWDG activated by software
IWDG_HW
(check only one option)
[ ] 1: IWDG activated by hardware
[ ] 0: LSI clock is not available as CPU clock source
LSI_EN
(check only one option)
[ ] 1: LSI clock is available as CPU clock source
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR register
HSITRIM
(check only one option)
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR register
OPT4 wakeup
[ ] for 16 MHz to 128 kHz prescaler
PRSC
(check only one option)
[ ] for 8 MHz to 128 kHz prescaler
[ ] for 4 MHz to 128 kHz prescaler
[ ] LSI clock source selected for AWU
CKAWUSEL
(check only one option)
[ ] HSE clock with prescaler selected as clock source for for
AWU
[ ] External crystal connected to OSCIN/OSCOUT
EXTCLK
(check only one option)
[ ] External clock signal on OSCIN
OPT5 crystal oscillator stabilization HSECNT (check only one option)
[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OPT6 is reserved
...........................................................................................................Comments:
...........................................................................................................Supply operating range in
the application:
...........................................................................................................Notes:
109/116DocID15590 Rev 8
Ordering informationSTM8S903K3 STM8S903F3