STM8S903K3 STM8S903F3 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM, 640 bytes EEPROM,10-bit ADC, 2 timers, UART, SPI, I²C - Switch-off peripheral clocks individually active, low consumption power-on • Permanently and power-down reset Interrupt management Nested interrupt controller with 32 interrupts LQFP32 7x7 UFQFPN32 5x5 • • Up to 28 external interrupts on 7 vectors SDIP32 400 mils Timers Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion an
Contents STM8S903K3 STM8S903F3 Contents 1 2 3 4 Introduction ..............................................................................................................8 Description ...............................................................................................................9 Block diagram ........................................................................................................10 Product overview .........................................................................
STM8S903K3 STM8S903F3 Contents 9 Unique ID ................................................................................................................49 10 Electrical characteristics ....................................................................................50 10.1 Parameter conditions .................................................................................................50 10.1.1 Minimum and maximum values .........................................................50 10.1.
List of tables STM8S903K3 STM8S903F3 List of tables Table 1. STM8S903K3/F3 access line features .......................................................................................9 Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14 Table 3. TIM timer features ....................................................................................................................16 Table 4. Legend/abbreviations for pinout tables .................
STM8S903K3 STM8S903F3 List of tables Table 48. ADC accuracy with RAIN < 10 kΩ , VDD= 5 V .........................................................................86 Table 49. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V ..............................................................87 Table 50. EMS data ................................................................................................................................89 Table 51. EMI data ....................................................
List of figures STM8S903K3 STM8S903F3 List of figures Figure 1. Block diagram .........................................................................................................................10 Figure 2. Flash memory organization ....................................................................................................13 Figure 3. STM8S903F3 TSSOP20/SO20 pinout ...................................................................................23 Figure 4. STM8S903F3 UFQFPN20 pinout .....
STM8S903K3 STM8S903F3 List of figures Figure 48. Recommended footprint for on-board emulation ..................................................................97 Figure 49. Recommended footprint without on-board emulation ...........................................................98 Figure 50. 32-lead shrink plastic DIP (400 ml) package ........................................................................98 Figure 51. 20-pin, 4.40 mm body, 0.65 mm pitch ................................................
Introduction 1 STM8S903K3 STM8S903F3 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). • information on programming, erasing and protection of the internal Flash memory • For please refer to the STM8S Flash programming manual (PM0051).
STM8S903K3 STM8S903F3 2 Description Description The STM8S903K3 and STM8S903F3 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost.
Block diagram 3 STM8S903K3 STM8S903F3 Block diagram Figure 1: Block diagram Reset block XTAL 1-16 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG 400 Kbit/s I 2C 8 Mbit/s SPI LIN master SPI emul. 8 Kbytes program Flash Debug/SWIM Address and data bus Single wire debug interf.
STM8S903K3 STM8S903F3 4 Product overview Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance.
Product overview STM8S903K3 STM8S903F3 SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.
STM8S903K3 STM8S903F3 Product overview program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.
Product overview - STM8S903K3 STM8S903F3 Up to 16 MHz high-speed user-external clock (HSE user-ext) 16 MHz high-speed internal RC oscillator (HSI) 128 kHz low-speed internal RC (LSI) clock: After reset, the microcontroller restarts by default with an internal 2 MHz • Startup clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. security system (CSS): This feature can be enabled by software.
STM8S903K3 STM8S903F3 Product overview Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.
Product overview STM8S903K3 STM8S903F3 module to control the timer with external signals or to synchronise with • Synchronization TIM5 or TIM6 • Break input to force the timer outputs into a defined state • Three complementary outputs with adjustable dead time • Encoder mode • Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.
STM8S903K3 STM8S903F3 Product overview • Conversion time: 14 clock cycles • Single and continuous and buffered continuous conversion modes • Buffer size (n x 10 bits) where n = number of input channels • Scan mode for single and continuous conversion of a sequence of channels • Analog watchdog capability with programmable upper and lower thresholds • Internal reference voltage on channel AIN7 • Analog watchdog interrupt • External trigger input • Trigger from TIM1 TRGO • End of conversion (EOC) interrupt
Product overview STM8S903K3 STM8S903F3 • Transmission error detection with interrupt generation • Parity control Synchronous communication Full duplex synchronous transfers • • SPI master operation • 8-bit data communication • Maximum speed: 1 Mbit/s at 16 MHz (f CPU/16) LIN master mode Emission: Generates 13-bit synch break frame • • Reception: Detects 11-bit break frame 4.14.
STM8S903K3 STM8S903F3 5 Pinout and pin description Pinout and pin description Table 4: Legend/abbreviations for pinout tables Type I= Input, O = Output, S = Power supply Level Input CM = CMOS Output HS = High sink Output speed O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Port and control configuration Reset state Input float = floating, wpu = weak pul
Pinout and pin description 5.
STM8S903K3 STM8S903F3 STM8S903F3 UFQFPN20 pinout 19 18 17 PD2(HS)/AIN3/[TIM5_CH3] PD5(HS)/AIN5/UART1_TX PD4 (HS)/BEEP / TIM5_CH1/UART1_CK 20 PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR PD6(HS)/AIN6/UART1_RX Figure 4: STM8S903F3 UFQFPN20 pinout 16 NRST 1 15 OSCIN/PA1 2 14 PC7(HS)/SPI_MISO/[TIM1_CH2] OSCOUT/PA2 3 13 PC6(HS)/SPI_MOSI/[TIM1_CH1] VSS 4 12 PC5 (HS)/SPI_SCK/[TIM5_CH1] VCAP 5 11 PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N] 9 PD1(HS)/SWIM 10 [TIM1_CH1N]/[TLI]/TIM1_CH3/(HS)PC3 8
Pinout and pin description 5.3 STM8S903K3 STM8S903F3 Pin description TSSOP20_SO20_UFQFPN20 Table 5: TSSOP20/SO20/UFQFPN20 pin description TSSOP UFQFPN Pin name SO20 4 Type Input floating 20 Output wpu Ext.
STM8S903K3 STM8S903F3 STM8S903K3 UFQFPN32/LQFP32/SDIP32 pinout VCAP VDD [UART1_TX] [SPI_NSS] TIM5_CH3/(HS) PA3 PB7 [UART1_RX] PF4 PD1 (HS)/SWIM PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR PD2 (HS)[AIN3] [TIM5_CH3] PD5 (HS)/AIN5/UART1_TX PD4 (HS)/BEEP/TIM5_CH1 [UART1_CK] PD0 (HS)/ TIM1_BKIN [CLK_CCO] PC7 (HS)/SPI_MISO [TIM1_CH2] PC6 (HS)/SPI_MOSI [TIM1_CH1] PC5 (HS)/SPI_SCK [TIM5_CH1] PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N] PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N] PC2 (HS)/TIM1_CH2 [TIM1_CH3N] PC1 (HS)/TIM1_C
Pinout and pin description STM8S903K3 STM8S903F3 Figure 6: STM8S903K3 SDIP32 pinout AIN4/TIM5_CH2/ADC_ETR/PD3(HS) TIM5_CH1[UART1_CK]BEEP/PD4(HS) AIN5/UART1_TX/PD5(HS) AIN6/UART1_RX/PD6(HS) [TIM1_CH4]TLI/PD7(HS) NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD [UART1_TX][SPI_NSS]/TIM5_CH3/PA3(HS) [UART1_RX]/PF4 PB7 PB6 [TIM1_BKIN]I2C_SDA/PB5(T) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PD2(HS)[AIN3][TIM5_CH3] PD1(HS)/SWIM PD0(HS)/TIM1_BKIN[CLK_CCO] PC7(HS)/SPI_MISO[TIM
STM8S903K3 STM8S903F3 SDIP UFQFPN/ Pin name 32 LQFP32 Pinout and pin description Type Input floating 15 10 PB6 I/O X 16 11 PB5/ I2C_SDA [TIM1_BKIN] I/O 17 12 PB4/ I2C_SCL [ADC_ETR] 18 13 19 Output wpu X Ext.
Pinout and pin description 5.6 STM8S903K3 STM8S903F3 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
STM8S903K3 STM8S903F3 Memory and register map 6 Memory and register map 6.1 Memory map Figure 7: Memory map 0x00 0000 RAM (1 Kbyte) 0x00 03FF 0x00 0800 513 bytes stack Reserved 0x00 3FFF 0x00 4000 0x00 427F 0x00 4280 0x00 47FF 0x00 4800 0x00 480A 0x00 480B 0x00 4864 0x00 4865 0x00 4870 0x00 4871 0x00 4FFF 0x00 5000 640 bytes data EEPROM Reserved Option bytes Reserved Unique ID Reserved GPIO and periph. reg.
Memory and register map STM8S903K3 STM8S903F3 6.2 Register map 6.2.
STM8S903K3 STM8S903F3 Address Block Memory and register map Reset status Register label Register name PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 5018 Port E Port F 0x00 501B (1) 0xXX (1) Depends on the external circuitry. 6.2.
Memory and register map Address 0x00 5064 0x00 5065 to STM8S903K3 STM8S903F3 Block Register label Register name Reset status Flash FLASH _DUKR Data EEPROM unprotection register 0x00 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reserved area (59 bytes) 0x00 509F 0x00 50A0 ITC 0x00 50A1 0x00 50A2 to Reserved area (17 bytes) 0x00 50B2 0x00 50B3 0x00 50B4 to RST RST_SR Reset status register 0xXX Reserved area (12 bytes) 0x00
STM8S903K3 STM8S903F3 Address Block 0x00 50CC 0x00 50CD 0x00 50CE to Memory and register map Register label Register name Reset status CLK_HSITRIMR HSI clock calibration trimming register 0x00 CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F Reserved area (3 bytes) 0x00 50D0 0x00 50D1 WWDG 0x00 50D2 0x00 50D3 to Reserved area (13 bytes) 00 50DF 0x00 50E0 IWDG 0x00 50E1 0x00 50E2 0x00 50E3 to IWDG_KR IWDG key
Memory and register map Address Block 0x00 5202 0x00 5203 0x00 5204 0x00 5205 0x00 5206 0x00 5207 0x00 5208 to STM8S903K3 STM8S903F3 Register label Register name Reset status SPI_ICR SPI interrupt control register 0x00 SPI_SR SPI status register 0x02 SPI_DR SPI data register 0x00 SPI_CRCPR SPI CRC polynomial register 0x07 SPI_RXCRCR SPI Rx CRC register 0xFF SPI_TXCRCR SPI Tx CRC register 0xFF Reserved area (8 bytes) 0x00 520F 2 0x00 5210 0x00 5211 0x00 5212 0x00 5213 0x00 5214 0x
STM8S903K3 STM8S903F3 Address Block 0x00 521C 0x00 521D 0x00 521E 0x00 521F to Memory and register map Register label Register name I2C_CCRH I C Clock control register high I2C_TRISER I C TRISE register I2C_PECR Reset status 2 0x00 2 0x02 I C packet error checking register 2 0x00 UART1_SR UART1 status register 0xC0 UART1_DR UART1 data register 0xXX UART1_BRR1 UART1 baud rate register 1 0x00 UART1_BRR2 UART1 baud rate register 2 0x00 UART1_CR1 UART1 control register 1 0x00
Memory and register map Address 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D 0x00 525E 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 34/116 Block STM8S903K3 STM8S903F3 Register label Register name Reset status TIM1_SMCR TIM1 slave mode control register 0x00 TIM1_ETR TIM1 external trigger register 0x00 TIM1_IER TIM1 interrupt enable register 0x00 TIM1_SR1 TIM1 status register 1 0x00 TIM1_SR
STM8S903K3 STM8S903F3 Address Block 0x00 5266 0x00 5267 0x00 5268 0x00 5269 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F 0x00 5270 to Memory and register map Register label Register name Reset status TIM1_CCR1L TIM1 capture/compare register 1 low 0x00 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00 TIM1_CCR3L TIM1 capture/compare register 3 low 0x00 TIM1_CCR4H
Memory and register map Address Block 0x00 5308 0x00 5309 Register label Register name Reset status TIM5_CCMR2 TIM5 capture/compare mode register 2 0x00 TIM5_CCMR3 TIM5 capture/compare mode register 3 0x00 TIM5_CCER1 0x00 530A TIM5_CCER2 0x00 530B 00 530C0x 0x00 530D 0x00 530E 0x00 530F 0x00 5310 0x00 5311 0x00 5312 0x00 5313 0x00 5314 0x00 5315 0x00 5316 0x00 5317 to STM8S903K3 STM8S903F3 TIM5 capture/compare enable register 1 TIM5 capture/compare enable register 2 0x00 0x00 TIM5_CNTRH
STM8S903K3 STM8S903F3 Address Block 0x00 5343 0x00 5344 0x00 5345 0x00 5346 0x00 5347 0x00 5348 0x00 5349 to Memory and register map Register label Register name Reset status TIM6_IER TIM6 interrupt enable register 0x00 TIM6_SR TIM6 status register 0x00 TIM6_EGR TIM6 event generation register 0x00 TIM6_CNTR TIM6 counter 0x00 TIM6_PSCR TIM6 prescaler register 0x00 TIM6_ARR TIM6 auto-reload register 0xFF ADC data buffer registers 0x00 ADC _CSR ADC control/status register 0x00 AD
Memory and register map Address Block 0x00 5409 0x00 540A 0x00 540B 0x00 540C 0x00 540D 0x00 540E 0x00 540F 0x00 5410 to STM8S903K3 STM8S903F3 Register label Register name Reset status ADC_HTRL ADC high threshold register low 0xFF ADC_LTRH ADC low threshold register high 0x00 ADC_LTRL ADC low threshold register low 0x00 ADC_AWSRH ADC analog watchdog status register high 0x00 ADC_AWSRL ADC analog watchdog status register low 0x00 ADC _AWCRH ADC analog watchdog control register high 0x00
STM8S903K3 STM8S903F3 Address Block Memory and register map Register label Register name Reset status 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CCR Condition code register 0x28 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 bytes) CPU CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF ITC_
Memory and register map Address 0x00 7F9A Block STM8S903K3 STM8S903F3 Register label Register name Reset status DM_ENFCTR DM enable function register 0xFF 0x00 7F9B to 0x00 7F9F (1) Reserved area (5 bytes) Accessible by debug module only 40/116 DocID15590 Rev 8
STM8S903K3 STM8S903F3 7 Interrupt vector mapping Interrupt vector mapping Table 10: Interrupt mapping IRQ Source no.
Interrupt vector mapping STM8S903K3 STM8S903F3 IRQ Source no.
STM8S903K3 STM8S903F3 8 Option bytes Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.
Option bytes Option byte no. STM8S903K3 STM8S903F3 Description Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Page 0 defined as UBC, memory write-protected 0x02: Pages 0 to 1 defined as UBC, memory write-protected. Page 0 and 1 contain the interrupt vectors. ...
STM8S903K3 STM8S903F3 Option byte no.
Option bytes STM8S903K3 STM8S903F3 Option byte no. (1) Description AFR5 Alternate function remapping option 5 (2) 0: AFR5 remapping option inactive: Default alternate function . 1: Port D0 alternate function = CLK_CCO. AFR4 Alternate function remapping option 4 (2) 0: AFR4 remapping option inactive: Default alternate functions . 1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN.
STM8S903K3 STM8S903F3 Option byte no. Option bytes (1) Description (2) 0: AFR3 remapping option inactive: Default alternate function . 1: Port C3 alternate function = TLI. AFR2 Alternate function remapping option 2 Reserved. (1) Do not use more than one remapping option in the same port. (2) Refer to pinout description.
Option bytes STM8S903K3 STM8S903F3 Table 16: STM8S903F3 alternate function remapping bits [1:0] for 20-pin packages AFR1 option bit value AFR0 option bit value I/O port 0 0 AFR1 and AFR0 remapping options inactive: (1) Default alternate functions 0 1 PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 1 1 (1) 48/116 0 1 PA3 Alternate function mapping SPI_NSS PD2 TIM5_CH3 PD2 TIM5_CH3 PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 PC2 — PC1 — PE5 TIM1_CH1N PA3 UART1_TX PF4 UART1_RX Re
STM8S903K3 STM8S903F3 9 Unique ID Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.
Electrical characteristics STM8S903K3 STM8S903F3 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
STM8S903K3 STM8S903F3 Electrical characteristics Figure 9: Pin input voltage STM8 pin VIN 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Electrical characteristics STM8S903K3 STM8S903F3 Symbol Ratings IVSS Total current out of VSS ground lines (sink) 80 IIO Output current sunk by any I/O and control pin 20 IINJ(PIN) (1) Max (2) Output current source by any I/Os and control pin - 20 Injected current on NRST pin ±4 Injected current on OSCIN pin ±4 Unit (3) (4) (5) ±4 Injected current on any other pin ΣI INJ(PIN) (3) (5) Total injected current (sum of all I/O and control pins) ± 20 (1) Data based on characterization
STM8S903K3 STM8S903F3 10.3 Electrical characteristics Operating conditions Table 21: General operating conditions Symbol Parameter fCPU Internal CPU clock frequency VDD VCAP (1) Conditions (3) TJ Unit 16 MHz Standard operating voltage 2.95 5.5 V CEXT: capacitance of external capacitor 470 3300 nF - 0.
Electrical characteristics (3) STM8S903K3 STM8S903F3 To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Thermal characteristics). Figure 10: fCPUmax versus VDD f CPU (MHz) Functionality 16 not guaranteed in this area 12 Functionality guaranteed @TA-40 to 125 °C 8 4 0 2.95 4.0 5.0 5.
STM8S903K3 STM8S903F3 Electrical characteristics Figure 11: External capacitor CEXT C ESR ESL Rleak 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as described in Pin input voltage. 10.3.2.
Electrical characteristics Symbol Parameter STM8S903K3 STM8S903F3 Conditions fCPU = fMASTER/128 = 125 kHz fCPU = fMASTER/128 = 15.625 kHz fCPU = fMASTER = 128 kHz (1) Typ Max HSI RC osc. (16 MHz) 0.72 0.9 HSI RC osc. (16 MHz/8) 0.46 0.58 LSI RC osc. (128 kHz) 0.42 0.57 (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off.
STM8S903K3 STM8S903F3 Symbol Parameter Electrical characteristics Conditions Typ (1) Max Unit 128 = 15.625 kHz fCPU = fMASTER = LSI RC osc. (128 kHz) 128 kHz (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.2 0.42 0.
Electrical characteristics Symbol Parameter STM8S903K3 STM8S903F3 Conditions Typ Max (1) Unit HSI RC osc. (16 MHz) fCPU = fMASTER/ 128 = HSI RC osc. 125 kHz (16 MHz) fCPU = fMASTER/ 128 = HSI RC osc. (2) 15.625 kHz (16 MHz/8) fCPU = fMASTER= LSI RC osc. 128 kHz (128 kHz) (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.3 0.89 1.1 0.7 0.88 0.45 0.57 0.4 0.
STM8S903K3 STM8S903F3 Electrical characteristics Conditions Symbol Parameter Main voltage regulator (2) (MVR) Supply current IDD(AH) in active halt mode (3) Flash mode Max Max at 85 at 125 °C °C Unit Typ Clock source (1) (1) 20 40 LSI RC osc. Power-down mode 10 (128 kHz) (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register.
Electrical characteristics 10.3.2.4 STM8S903K3 STM8S903F3 Total current consumption in halt mode Table 29: Total current consumption in halt mode at VDD = 5 V Symbol Parameter Conditions Typ Supply current in halt mode Flash in operating mode, HSI clock after wakeup 63 IDD(H) (1) Max at Max at (1) (1) 85 °C 125 °C 75 Unit 105 μA Flash in power-down mode, HSI clock after wakeup 6.
STM8S903K3 STM8S903F3 Symbol Parameter Conditions Wakeup time active MVR voltage halt mode to run regulator (3) (4) Typ Flash in operating (5) mode Wakeup time active MVR voltage Flash in HSI halt mode to run regulator (after power-down (5) off Wakeup time from Flash in operating mode mode (6) - (6) - 48 50 wakeup) (5) halt mode to run (3) Unit wakeup) mode mode (5) Flash in power-down mode (1) Data guaranteed by design, not tested in production.
Electrical characteristics STM8S903K3 STM8S903F3 HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V Table 33: Peripheral current consumption Symbol Parameter Typ.
STM8S903K3 STM8S903F3 Electrical characteristics Figure 13: Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V Figure 14: Typ IDD(RUN) vs.
Electrical characteristics STM8S903K3 STM8S903F3 Figure 15: Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz Figure 16: Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V Figure 17: Typ IDD(WFI) vs.
STM8S903K3 STM8S903F3 10.3.3 Electrical characteristics External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 34: HSE user external clock characteristics Symbol Parameter fHSE_ext User external clock source frequency 0 16 OSCIN input pin high level voltage 0.7 x VDD VDD + 0.3 V OSCIN input pin low level voltage VSS 0.
Electrical characteristics STM8S903K3 STM8S903F3 Symbol Parameter RF Feedback resistor (1) C Conditions Min Typ Max Unit - 220 - kΩ - - 20 pF - - Recommended load (2) capacitance IDD(HSE) HSE oscillator power consumption C = 20 pF, 6 (startup) (3) fOSC = 16 MHz 1.6 (stabilized) mA C = 10 pF, - 6 (startup) - (3) fOSC =16 MHz gm 1.
STM8S903K3 STM8S903F3 Electrical characteristics Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1= CL2 = C: Grounded external capacitance gm >> gmcrit 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA.
Electrical characteristics STM8S903K3 STM8S903F3 Figure 20: Typical HSI frequency variation vs VDD @ 4 temperatures Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA.
STM8S903K3 STM8S903F3 10.3.5 Electrical characteristics Memory characteristics RAM and hardware registers Table 38: RAM and hardware registers Symbol Parameter VRM Data retention mode (1) Conditions Min Unit Halt mode (or reset) VIT-max (2) V (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
Electrical characteristics STM8S903K3 STM8S903F3 Symbol Parameter Conditions Typ Max 1 - - - 2 - (1) Min Unit Data retention (data memory) after 300k erase/write cycles at TRET = 85°C TA = +125 °C IDD Supply current (Flash programming or erasing mA for 1 to 128 bytes) (1) Data based on characterization results, not tested in production. (2) The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.
STM8S903K3 STM8S903F3 Symbol Electrical characteristics Parameter Conditions Min Typ Max Unit - - 50 (3) (2) Load = 20 pF Standard and high sink I/Os Load = 20 pF Ilkg Digital input leakage current VSS ≤ VIN ≤VDD - - ±1 Ilkg ana Analog input leakage current VSS ≤ VIN ≤ VDD - - ±250 - - ±1 Ilkg(inj) Leakage current in adjacent I/O Injection current ±4 mA (2) (2) μA nA μA (1) Hysteresis voltage between Schmitt trigger switching levels.
Electrical characteristics STM8S903K3 STM8S903F3 Figure 23: Typical pull-up resistance vs VDD @ 4 temperatures Figure 24: Typical pull-up current vs VDD @ 4 temperatures Table 41: Output driving current (standard ports) Symbol Parameter Conditions Output low level with 8 pins sunk IIO= 10 mA, VDD = 5 V VOL Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V VOH 72/116 Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V DocID15590 Rev 8 Min Max - 2.0 - 2.8 (1) 1.
STM8S903K3 STM8S903F3 Electrical characteristics Symbol Parameter Conditions Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V (1) Min Max (1) 2.1 Unit - Data based on characterization results, not tested in production Table 42: Output driving current (true open drain ports) Symbol (1) Parameter Conditions Max VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 5 V VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 3.3 V 1.
Electrical characteristics STM8S903K3 STM8S903F3 Figure 25: Typ. VOL @ VDD = 5 V (standard ports) Figure 26: Typ. VOL @ VDD = 3.
STM8S903K3 STM8S903F3 Electrical characteristics Figure 27: Typ. VOL @ VDD = 5 V (true open drain ports) Figure 28: Typ. VOL @ VDD = 3.
Electrical characteristics STM8S903K3 STM8S903F3 Figure 29: Typ. VOL @ VDD = 5 V (high sink ports) Figure 30: Typ. VOL @ VDD = 3.
STM8S903K3 STM8S903F3 Electrical characteristics Figure 31: Typ. VDD - VOH@ VDD = 5 V (standard ports) Figure 32: Typ. VDD - VOH @ VDD = 3.
Electrical characteristics STM8S903K3 STM8S903F3 Figure 33: Typ. VDD - VOH@ VDD = 5 V (high sink ports) Figure 34: Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) 10.3.7 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 44: NRST pin characteristics Symbol Parameter Conditions VIL(NRST) NRST input low (1) Min -0.3 level voltage 78/116 DocID15590 Rev 8 Typ Max - 0.
STM8S903K3 STM8S903F3 Electrical characteristics Symbol Parameter Conditions VIH(NRST) NRST input high (1) level voltage VOL(NRST) IOL=2 mA Typ (2) Unit - VDD + 0.3 - - 0.5 30 55 80 - - 75 (1) NRST pull-up Max 0.
Electrical characteristics STM8S903K3 STM8S903F3 Figure 36: Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 37: Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table 40: I/O static characteristics ), otherwise the reset is not taken into account internally.
STM8S903K3 STM8S903F3 Electrical characteristics Figure 38: Recommended reset pin protection STM8 VDD RPU External reset circuit NRST Internal reset Filter 0.1 μF (optional) 10.3.8 SPI serial peripheral interface Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER.
Electrical characteristics Symbol ta(SO) (3) (4) STM8S903K3 STM8S903F3 Parameter (1) Conditions Data output Min Slave mode (3) (5) tMASTER Data output Slave mode 25 disable time tv(SO) (3) Data output valid Slave mode time tv(MO) th(SO) th(MO) (3) (3) (3) Unit 3x access time tdis(SO) Max (2) 65 (after enable edge) Data output valid Master mode time (after enable edge) Data output hold Slave mode time (after enable edge) Data output hold Master mode time (after enable e
STM8S903K3 STM8S903F3 Electrical characteristics Figure 39: SPI timing diagram - slave mode and CPHA = 0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN B I T1 IN LSB IN th(SI) ai14134 Figure 40: SPI timing diagram - slave mode and CPHA = 1 NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL)
Electrical characteristics STM8S903K3 STM8S903F3 (1) Figure 41: SPI timing diagram - master mode High NSS input SCK output SCK output tc(SCK) CPHA= 0 CPOL=0 CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INP UT tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136b 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 10.3.
STM8S903K3 STM8S903F3 Electrical characteristics Symbol Parameter 2 (2) STOP condition setup time tw(STO:STA) STOP to START condition time (bus free) Cb Fast mode I C (2) Min tsu(STO) 2 (1) Standard mode I C (2) Max Unit (2) Min Max 4.0 - 0.6 - 4.7 - 1.
Electrical characteristics STM8S903K3 STM8S903F3 Symbol Parameter Conditions Min Typ Max 1 - 6 VSS - VDD V 1.19 1.22 1.25 V - 3 - pF fADC = 4 MHz - 0.75 - µs fADC = 6 MHz - 0.5 - - 7 - VDD =4.5 to 5.5 V VAIN (1) Conversion voltage range VBGREF Internal bandgap reference voltage CADC tS (1) VDD =2.95 to 5.
STM8S903K3 STM8S903F3 Symbol |EL| (1) Electrical characteristics Parameter Conditions (2) Integral linearity error Typ (1) Max fADC = 6 MHz 0.7 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.8 2 fADC = 6 MHz 0.8 2 Unit Data based on characterisation results, not tested in production. (2) ADC accuracy vs.
Electrical characteristics STM8S903K3 STM8S903F3 Figure 43: ADC accuracy characteristics 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one.
STM8S903K3 STM8S903F3 10.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 10.3.11.1 Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
Electrical characteristics STM8S903K3 STM8S903F3 (1) Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). 10.3.11.3 Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE IEC 61967-2 which specifies the board and the loading of each pin.
STM8S903K3 STM8S903F3 Electrical characteristics Human body model. This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
Package information 11 STM8S903K3 STM8S903F3 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 11.
STM8S903K3 STM8S903F3 Dim. Package information (1) mm Min D3 inches Typ Max Min 5.600 Typ Max 0.2205 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.600 0.2205 e 0.800 0.0315 L 0.450 L1 0.750 0.0177 1.000 k 0.0° ccc (1) 0.600 3.5° 0.0236 0.0295 0.0394 7.0° 0.0° 3.5° 0.100 7.0° 0.
Package information 11.2 STM8S903K3 STM8S903F3 32-lead UFQFPN package mechanical data Figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) AOB8_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. 4. Dimensions are in millimeters.
STM8S903K3 STM8S903F3 Dim. Package information (1) mm inches Min Typ Max Typ Max b 0.180 0.250 0.300 0.0071 0.0098 0.0118 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D2 3.200 3.450 3.700 0.1260 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e 0.300 0.0197 0.400 0.500 ddd (1) 0.1457 0.500 L 11.3 Min 0.0118 0.0157 0.080 0.0197 0.0031 Values in inches are converted from mm and rounded to 4 decimal digits.
Package information STM8S903K3 STM8S903F3 1. Drawing is not to scale. Table 56: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data Dim. Min inches Typ Max Min Typ D 3.000 0.1181 E 3.000 0.1181 Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 0.152 0.0060 e 0.500 0.0197 L1 0.500 0.550 0.600 0.0197 0.0217 0.0236 L2 0.300 0.350 0.400 0.0118 0.0138 0.0157 L3 0.150 0.0059 L4 0.
STM8S903K3 STM8S903F3 11.4 Package information UFQFPN recommended footprint Figure 48: Recommended footprint for on-board emulation 0.5mm 0.8mm [0.032"] 4mm [0.157"] 0.5mm 1.65mm [0.065"] 0.9mm [0.035"] 0.3mm [0.012"] 4mm [0.157"] ai15319 Bottom view 1.
Package information STM8S903K3 STM8S903F3 Figure 49: Recommended footprint without on-board emulation 1. Drawing is not to scale 2. Dimensions are in millimeters 11.
STM8S903K3 STM8S903F3 Package information Table 57: 32-lead shrink plastic DIP (400 ml) package mechanical data Dim. (1) mm Min inches Typ 3.759 Max A 3.556 5.080 A1 0.508 A2 3.048 3.556 4.572 B 0.356 0.457 B1 0.762 C Min 0.1400 Typ Max 0.1480 0.2000 0.1200 0.1400 0.1800 0.584 0.0140 0.0180 0.0230 1.016 1.397 0.0300 0.0400 0.0550 0.203 0.254 0.356 0.0079 0.0100 0.0140 D 27.430 27.940 28.450 1.0799 1.1000 1.1201 E 9.906 10.410 11.050 0.3900 0.4098 0.
Package information 11.6 STM8S903K3 STM8S903F3 20-pin TSSOP package mechanical data Figure 51: 20-pin, 4.40 mm body, 0.65 mm pitch D 20 11 c E1 1 E 10 k aaa CP A1 A L A2 L1 b e YA_ME Table 58: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data Dim. (1) mm Min inches Typ A Min Typ 1.200 A1 0.050 A2 0.800 b Max 0.0472 0.150 0.0020 1.050 0.0315 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 D 6.400 6.500 6.600 0.2520 0.2559 0.2598 E 6.200 6.400 6.
STM8S903K3 STM8S903F3 Dim. Package information (1) mm inches Min k Typ Max 0.0° 8.0° aaa (1) 11.7 Min Typ Max 0.0° 8.0° 0.100 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits 20-pin SO package mechanical data Figure 52: 20-lead, plastic small outline (300 mils) package D 20 11 h x 45° C E 1 H 10 A B ddd A1 e A1 k L Z7_ME Table 59: 20-lead, plastic small outline (300 mils) mechanical data Dim. (1) mm Min inches Typ Max Min Typ Max A 2.
Package information Dim. STM8S903K3 STM8S903F3 (1) mm inches Min Typ Max Typ Max H 10.000 10.650 0.3937 0.4193 h 0.250 0.750 0.0098 0.0295 L 0.400 1.270 0.0157 0.0500 k 0.0° 8.0° 0.0° 8.0° ddd (1) 11.8 Min 0.100 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits Thermal characteristics The maximum chip junction temperature (TJ max) must never exceed the values given in Operating conditions.
STM8S903K3 STM8S903F3 Symbol ΘJA ΘJA ΘJA Package information (1) Parameter Value Thermal resistance junction-ambient UFQFPN20 - 3 x 3 mm Thermal resistance junction-ambient LQFP32 - 7 x 7 mm Thermal resistance junction-ambient 101 60 Unit °C/W °C/W 38 °C/W 60 °C/W UFQFPN32 - 5 x 5 mm ΘJA Thermal resistance junction-ambient SDIP32 - 400 mils (1) Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 11.8.
Ordering information 12 STM8S903K3 STM8S903F3 Ordering information Figure 53: STM8S903K3/F3 ordering information scheme Example: STM8 S 903 K 3 T 6 TR Product class STM8 microcontroller Family type S = Standard Sub-family type 903 = 903 sub-family Pin count K = 32 pins F = 20 pins Program memory size 3 = 8 Kbytes Package type 1 B = SDIP T = LQFP U = UFQFPN P = TSSOP M = SO Temperature range 3 = -40 °C to 125 °C 6 = -40 °C to 85 °C Package pitch Blank = 0.5 or 0.65 mm C = 0.
STM8S903K3 STM8S903F3 Ordering information Customer ........................................................................................................... Address ........................................................................................................... Contact ........................................................................................................... Phone no. .....................................................................................................
Ordering information STM8S903K3 STM8S903F3 Padding value for unused program memory (check only one option) [ ]0xFF Fixed value [ ]0x83 TRAP instruction opcode [ ]0x75 Illegal opcode (causes a reset when executed) OPT0 memory readout protection (check only one option) [ ] Disable or [ ] Enable OPT1 user boot code area (UBC) 0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below.
STM8S903K3 STM8S903F3 AFR1, AFR0 (check only one option) Ordering information [ ] 00: Remapping options inactive. Default alternate functions used. Refer to pinout description. [ ] 01: Port C5 alternate function = TIM5_CH1, port C6 alternate function = TIM1_CH1, and port C7 alternate function = TIM1_CH2. [ ] 10: Port A3 alternate function = SPI_NSS and port D2 alternate function = TIM5_CH3.
Ordering information STM8S903K3 STM8S903F3 OPT2 alternate function remapping for STM8S903F3 Do not use more than one remapping option in the same port. AFR1, AFR0 (check only one option) [ ] 00: Remapping options inactive. Default alternate functions used. Refer to pinout description. [ ] 01: Port C5 alternate function = TIM5_CH1, port C6 alternate function = TIM1_CH1, and port C7 alternate function = TIM1_CH2. [ ] 10: Port A3 alternate function = SPI_NSS and port D2 alternate function = TIM5_CH3.
STM8S903K3 STM8S903F3 IWDG_HW (check only one option) LSI_EN (check only one option) HSITRIM (check only one option) Ordering information [ ] 0: IWDG activated by software [ ] 1: IWDG activated by hardware [ ] 0: LSI clock is not available as CPU clock source [ ] 1: LSI clock is available as CPU clock source [ ] 0: 3-bit trimming supported in CLK_HSITRIMR register [ ] 1: 4-bit trimming supported in CLK_HSITRIMR register OPT4 wakeup PRSC (check only one option) [ ] for 16 MHz to 128 kHz prescaler [ ] fo
STM8 development tools 13 STM8S903K3 STM8S903F3 STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 13.
STM8S903K3 STM8S903F3 13.2.1 STM8 development tools STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu.
Revision history 14 STM8S903K3 STM8S903F3 Revision history Table 61: Document revision history Date Revision Changes 30-Apr-2009 1 Initial revision 03-Jun-2009 2 Added bullet point concerning unique identifier to Features section on cover page. Highlighted internal reference voltage in Analog-to-digital converter (ADC1) section. Updated wpu and PP status of PB5/12C_SDA[TIM1_BKIN] and PB4/12C_SCL[ADC_ETR] pins in Pin description. Updated Figure 7: Memory map. Added Unique ID section.
STM8S903K3 STM8S903F3 Date Revision history Revision Changes Updated ΘJA in Table 15: STM8S903K3 alternate function remapping bits [1:0] for 32-pin packages. Changed ΘJA to 60°C/W in Selecting the product temperature range section. Ordering information: replaced package pitch digit by VFQFPN/UFQFPN package, and added footnote regarding possible future release of a dedicated ordering information scheme. Added SO20W, TSSOP20, SDIP32, and UFQFPN32. Added STM8S903K3/F3 FASTROM microcontroller option list.
Revision history Date STM8S903K3 STM8S903F3 Revision Changes Updated "special marking" and "OPT2 alternate function remapping" sections in the STM8S903K3/F3 FASTROM microcontroller option list. 28-Jul-2011 6 Added note for OPT1 option list. Updated OPT2 option list for STM8S903K3 and created OPT2 option list for STM8S903F3 in STM8S903K3/F3 FASTROM microcontroller option list.
STM8S903K3 STM8S903F3 Date Revision history Revision Changes Modified Figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) to add package top view.
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