Datasheet

Alternate function after remap
[option bit]
Default alternate functionMain
function
(after
reset)
OutputInput
TypePin nameUFQFPN/
LQFP32
SDIP
32
PPODSpeedHigh
sink
(1)
Ext.
interrupt
wpufloating
Port
B6
XXO1XXXI/OPB61015
Timer 1 - break input [AFR4]I
2
C dataPort
B5
T
(3)
O1XXI/OPB5/ I2C_SDA [TIM1_BKIN]1116
ADC external trigger [AFR4]I
2
C clockPort
B4
T
(3)
O1XXI/OPB4/ I2C_SCL [ADC_ETR]1217
Analog input 3/ Timer 1
external trigger
Port
B3
XXO3HSXXXI/OPB3/ AIN3/TIM1_ETR1318
Analog input 2/ Timer 1 -
inverted channel 3
Port
B2
XXO3HSXXXI/OPB2/ AIN2/ TIM1_CH3N1419
Analog input 1/ Timer 1 -
inverted channel 2
Port
B1
XXO3HSXXXI/OPB1/ AIN1/ TIM1_CH2N1520
Analog input 0/ Timer 1 -
inverted channel 1
Port
B0
XXO3HSXXXI/OPB0/ AIN0/ TIM1_CH1N1621
Timer 1 - inverted channel 1
[AFR1:0]
SPI master/ slave selectPort
E5
XXO3HSXXXI/OPE5/ SPI_NSS [TIM1_CH1N]1722
Timer 1 - inverted channel 2
[AFR1:0]
Timer 1 - channel 1
UART1 clock
Port
C1
XXO3HSXXXI/OPC1/ TIM1_CH1/ UART1_CK
[TIM1_CH2N]
1823
Timer 1 - inverted channel 3
[AFR1:0]
Timer 1 - channel 2Port
C2
XXO3HSXXXI/OPC2/ TIM1_CH2 [TIM1_CH3N]1924
Top level interrupt [AFR3] Timer
1 inverted channel 1 [AFR7]
Timer 1 - channel 3Port
C3
XXO3HSXXXI/OPC3/ TIM1_CH3/TLI/[TIM1_CH1N
]
2025
Analog input 2 [AFR2]Timer 1
inverted channel 2 [AFR7]
Timer 1 - channel 4
/configurable clock output
Port
C4
XXO3HSXXXI/OPC4/ TIM1_CH4/
CLK_CCO/AIN2/[TIM1_CH2N]
2126
Timer 5 channel 1 [AFR0]SPI clockPort
C5
XXO3HSXXXI/OPC5/SPI_SCK [TIM5_CH1]2227
Timer 1 channel 1 [AFR0]PI master out/slave inPort
C6
XXO3HSXXXI/OPC6/ SPI_MOSI [TIM1_CH1]2328
Timer 1 channel 2[AFR0]SPI master in/ slave outPort
C7
XXO3HSXXXI/OPC7/ SPI_MISO [TIM1_CH2]2429
Configurable clock output
[AFR5]
Timer 1 - break inputPort
D0
XXO3HSXXXI/OPD0/ TIM1_BKIN [CLK_CCO]2530
SWIM data interfacePort
D1
XXO4HSXXXI/O
PD1/ SWIM
(4)
2631
Analog input 3 [AFR2] Timer 52
- channel 3 [AFR1]
Port
D2
XXO3HSXXXI/OPD2/AIN3/ [TIM5_CH3]2732
Analog input 4 Timer 52 -
channel 2/ADC external
trigger
Port
D3
XXO3HSXXXI/OPD3/ AIN4/ TIM5_CH2/ ADC_ETR281
UART clock [AFR2]Timer 5 - channel 1/BEEP
output
Port
D4
XXO3HSXXXI/OPD4/ TIM5_CH1/ BEEP
[UART1_CK]
292
Analog input 5/ UART1
data transmit
Port
D5
XXO3HSXXXI/OPD5/ AIN5/ UART1_TX303
Analog input 6/ UART1
data receive
Port
D6
XXO3HSXXXI/OPD6/ AIN6/ UART1_RX314
Timer 1 - channel 4 [AFR6]Top level interruptPort
D7
XXO3HSXXXI/OPD7/ TLI [TIM1_CH4]325
(1)
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section
"Absolute maximum ratings").
(2)
When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
(3)
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V
DD
are not implemented)
(4)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
25/116DocID15590 Rev 8
Pinout and pin descriptionSTM8S903K3 STM8S903F3