Datasheet

Pin description TSSOP20_SO20_UFQFPN205.3
Table 5: TSSOP20/SO20/UFQFPN20 pin description
Alternate function after remap
[option bit]
Default alternate functionMain
function
(after
reset)
OutputInput
TypePin nameUFQFPN
20
TSSOP
SO20
PPODSpeedHigh
sink
(1)
Ext.
interrupt
wpufloating
ResetXI/ONRST14
Resonator/ crystal inPort
A1
XXO1XXXI/O
PA1/ OSCIN
(2)
25
Resonator/ crystal outPort
A2
XXO1XXXI/OPA2/ OSCOUT36
Digital groundSV
SS
47
1.8 V regulator capacitorSVCAP58
Digital power supplySV
DD
69
SPI master/ slave select [AFR1]/
UART1 data transmit [AFR1:0]
Timer 52 channel 3Port
A3
XXO3HSXXXI/OPA3/ TIM5_CH3 [SPI_NSS]
[UART1_TX]
710
Timer 1 - break input [AFR4]I
2
C dataPort
B5
T
(3)
O1XXI/OPB5/ I2C_SDA [TIM1_BKIN]811
ADC external trigger [AFR4]I
2
C clockPort
B4
T
(3)
O1XXI/OPB4/ I2C_SCL [ADC_ETR]912
Top level interrupt [AFR3] Timer
1 inverted channel 1 [AFR7]
Timer 1 - channel 3Port
C3
XXO3HSXXXI/OPC3/
TIM1_CH3/TLI/[TIM1_CH1N ]
1013
Analog input 2 [AFR2]Timer 1
inverted channel 2 [AFR7]
Timer 1 - channel 4
/configurable clock output
Port
C4
XXO3HSXXXI/OPC4/ TIM1_CH4/
CLK_CCO/AIN2/[TIM1_CH2N]
1114
Timer 5 channel 1 [AFR0]SPI clockPort
C5
XXO3HSXXXI/OPC5/SPI_SCK [TIM5_CH1]1215
Timer 1 channel 1 [AFR0]PI master out/slave inPort
C6
XXO3HSXXXI/OPC6/ SPI_MOSI [TIM1_CH1]1316
Timer 1 channel 2[AFR0]SPI master in/ slave outPort
C7
XXO3HSXXXI/OPC7/ SPI_MISO [TIM1_CH2]1417
SWIM data interfacePort
D1
XXO4HSXXXI/O
PD1/ SWIM
(4)
1518
Analog input 3 [AFR2] Timer 52
- channel 3 [AFR1]
Port
D2
XXO3HSXXXI/OPD2/AIN3/ [TIM5_CH3]1619
Analog input 4 Timer 52 -
channel 2/ADC external
trigger
Port
D3
XXO3HSXXXI/OPD3/ AIN4/ TIM5_CH2/
ADC_ETR
1720
UART clock [AFR2]Timer 5 - channel 1/BEEP
output
Port
D4
XXO3HSXXXI/OPD4/ TIM5_CH1/ BEEP
[UART1_CK]
181
Analog input 5/ UART1
data transmit
Port
D5
XXO3HSXXXI/OPD5/ AIN5/ UART1_TX192
Analog input 6/ UART1
data receive
Port
D6
XXO3HSXXXI/OPD6/ AIN6/ UART1_RX203
(1)
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section
"Absolute maximum ratings").
(2)
When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
(3)
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V
DD
are not implemented)
(4)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
DocID15590 Rev 822/116
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