Datasheet

Block diagram3
Figure 1: Block diagram
XTAL 1-16 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
I
2
C
SPI
UART1
16-bit general purpose
AWU timer
Reset block
Reset
POR
BOR
Clock controller
Detector
Clock to peripherals and core
8 Mbit/s
LIN master
Address and data bus
Window WDG
8 Kbytes
640 bytes
1 Kbytes
ADC1
4 CAPCOM
Reset
400 Kbit/s
Single wire
debug interf.
SPI emul.
channels
program
Flash
16-bit advanced control
timer (TIM1)
8-bit basic timer
data EEPROM
RAM
Up to
Beeper
1/2/4 kHz
beep
Independent WDG
(TIM6)
3 CAPCOM
channels
Up to
+ 3 complementary
outputs
Timer (TIM5)
Up to 7
channels
DocID15590 Rev 810/116
STM8S903K3 STM8S903F3Block diagram