Datasheet

STM8S207xx, STM8S208xx Electrical characteristics
Doc ID 14733 Rev 12 79/103
Figure 39. SPI timing diagram - master mode
(1)
1. Measurement points are done at CMOS levels: 0.3 V
DD
and 0.7 V
DD.
ai14136
SCK Input
CPHA= 0
MOSI
OUTUT
MISO
INP UT
CPHA= 0
MSBIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK Input
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)