Datasheet

Electrical characteristics STM8S207xx, STM8S208xx
76/103 Doc ID 14733 Rev 12
Figure 34. Typical NRST pull-up resistance vs V
DD
@ 4 temperatures
Figure 35. Typical NRST pull-up current vs V
DD
@ 4 temperatures
The reset network shown in Figure 36 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V
IL
max. level specified in
Tabl e 41. Otherwise the reset is not taken into account internally. For power consumption
sensitive applications, the capacity of the external reset capacitor can be reduced to limit
charge/discharge current. If the NRSTsignal is used to reset the external circuitry, care must
be taken of the charge/discharge time of the external capacitor to fulfill the external device’s
reset timing conditions. The minimum recommended capacity is 10 nF.
Figure 36. Recommended reset pin protection
30
35
40
45
50
55
60
2.5 3 3.5 4 4.5 5 5.5 6
-40˚C
25˚C
85˚C
125˚C
V DD [V]
NRESET pull-up resistance [ΩW]
0
20
40
60
80
100
120
140
0123456
V
DD
[V]
NRESET Pull-Up current [µA]
-40˚C
25˚C
85˚C
125˚C
ai15069
0.1µF
External
reset
circuit
STM8
Filter
R
PU
V
DD
Internal reset
NRST
(optional)