Datasheet

Electrical characteristics STM8S207xx, STM8S208xx
56/103 Doc ID 14733 Rev 12
Figure 12. f
CPUmax
versus V
DD
10.3.1 VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
EXT
to the
V
CAP
pin. C
EXT
is specified in Tabl e 18. Care should be taken to limit the series inductance
to less than 15 nH.
Figure 13. External capacitor C
EXT
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
Table 19. Operating conditions at power-up/power-down
Symbol Parameter Conditions Min Typ Max Unit
t
VDD
V
DD
rise time rate 2
(1)
1. Guaranteed by design, not tested in production.
∞
µs/V
V
DD
fall time rate 2
(1)
∞
t
TEMP
Reset release
delay
V
DD
rising 1.7
(1)
ms
V
IT+
Power-on reset
threshold
2.65 2.8 2.95 V
V
IT-
Brown-out reset
threshold
2.58 2.73 2.88 V
V
HYS(BOR)
Brown-out reset
hysteresis
70 mV
f
CPU
[MHz]
SUPPLY VOLTAGE [V]
24
12
8
4
0
2.95 4.0 5.0
FUNCTIONALITY
FUNCTIONALITY
GUARANTEED
@ T
A
-40 to 125 °C
NOT GUARANTEED
IN THIS AREA
16
5.5
FUNCTIONALITY GUARANTEED
@ T
A
-40 to 105 °C
C
Rleak
ESR ESL