Datasheet

STM8S207xx, STM8S208xx Memory and register map
Doc ID 14733 Rev 12 41/103
0x00 532B
TIM3
TIM3_ARRH TIM3 auto-reload register high 0xFF
0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF
0x00 532D TIM3_CCR1H TIM3 capture/compare register 1 high 0x00
0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00
0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00
0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00
0x00 5331 to
0x00 533F
Reserved area (15 bytes)
0x00 5340
TIM4
TIM4_CR1 TIM4 control register 1 0x00
0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00
0x00 5342 TIM4_SR TIM4 status register 0x00
0x00 5343 TIM4_EGR TIM4 event generation register 0x00
0x00 5344 TIM4_CNTR TIM4 counter 0x00
0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00
0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF
0x00 5347 to
0x00 53FF
Reserved area (185 bytes)
0x00 5400
ADC2
ADC _CSR ADC control/status register 0x00
0x00 5401 ADC_CR1 ADC configuration register 1 0x00
0x00 5402 ADC_CR2 ADC configuration register 2 0x00
0x00 5403 ADC_CR3 ADC configuration register 3 0x00
0x00 5404 ADC_DRH ADC data register high 0xXX
0x00 5405 ADC_DRL ADC data register low 0xXX
0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00
0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00
0x00 5408 to
0x00 541F
Reserved area (24 bytes)
0x00 5420
beCAN
CAN_MCR CAN master control register 0x02
0x00 5421 CAN_MSR CAN master status register 0x02
0x00 5422 CAN_TSR CAN transmit status register 0x00
0x00 5423 CAN_TPR CAN transmit priority register 0x0C
0x00 5424 CAN_RFR CAN receive FIFO register 0x00
0x00 5425 CAN_IER CAN interrupt enable register 0x00
0x00 5426 CAN_DGR CAN diagnosis register 0x0C
0x00 5427 CAN_FPSR CAN page selection register 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name
Reset
status