Datasheet

Block diagram STM8S207xx, STM8S208xx
12/103 Doc ID 14733 Rev 12
3 Block diagram
Figure 1. STM8S20xxx performance line block diagram
1. Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
Independent WDG: Independent watchdog
POR/PDR: Power on reset / power down reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
UART: Universal asynchronous receiver transmitter
Window WDG: Window watchdog
XTAL 1-24 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8 core
Debug/SWIM
I
2
C
SPI
UART1
UART3
AWU timer
Reset block
Reset
Clock controller
Detector
Clock to peripherals and core
10 Mbit/s
LIN master
16 channels
Address and data bus
Window WDG
Up to 128 Kbytes
Up to 2 Kbytes
Up to 6 Kbytes
Boot ROM
ADC2
beCAN
Reset
400 Kbit/s
1 Mbit/s
Master/slave
Single wire
autosynchro
debug interf.
SPI emul.
high density program
Flash
data EEPROM
RAM
16-bit general purpose
16-bit advanced control
timer (TIM1)
timers (TIM2, TIM3)
8-bit basic timer
(TIM4)
Beeper
1/2/4 kHz
beep
Independent WDG
4 CAPCOM
channels
Up to
5 CAPCOM
channels
Up to
+ 3 complementary
outputs
POR/PDR
BOR