Datasheet

Revision history STM8S207xx, STM8S208xx
102/103 Doc ID 14733 Rev 12
14-Sep-2010 10
Added part number STM8S208M8 to Table 1: Device summary.
Updated "reset state" of Table 5: Legend/abbreviations for pinout
table.
Added footnote 4 to Table 6: Pin description.
Table 9: General hardware register map: standardized all reset state
values; updated the reset state values of RST_SR, CLK_SWCR,
CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR, and ADC_DRx
registers; added the reset values of the CAN paged registers.
Figure 36: Recommended reset pin protection: replaced 0.01 µF with
0.1 µF.
Figure 40: Typical application with I2C bus and timing diagram:
t
w(SCKH)
, t
w(SCKL)
, t
r(SCK)
, and t
f(SCK)
replaced by t
w(SCLH)
, t
w(SCLL)
,
t
r(SCL)
, and t
f(SCL)
respectively.
22-Mar-2011 11
Table 1: Device summary: added STM8S207K8.
Table 2: STM8S20xxx performance line features: added
STM8S207K8 device and changed the RAM value of all other
devices to 6 Kbytes.
Figure 3, Figure 4, Figure 5, and Figure 7: removed TIM1_CH4 from
pins 80, 64, 48, and 32 respectively.
Table 6: Pin description: updated note 3 and added note 5.
Table 9: General hardware register map: removed I2C_PECR
register.
Section 10.3.7: Reset pin characteristics: added text regarding the
rest network.
10-Feb-2012 12
Figure 1: STM8S20xxx performance line block diagram: updated
POR/PDR and BOR; updated LINUART input; added legend.
Table 18: General operating conditions: updated V
CAP
.
Table 26: Total current consumption in halt mode at VDD = 5 V:
updated title, modified existing max column, and added new max
column (at 125 °C) with data.
Table 37: I/O static characteristics: added new condition and new
max values for rise and fall time; added footnote 3; updated typ and
max pull-up resistor values.
Section 10.3.7: Reset pin characteristics: updated cross reference in
text below Figure 35
Table 41: NRST pin characteristics: updated typ and max values of
the NRST pull-up resistor.
Table 58. Document revision history (continued)
Date Revision Changes