Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 44 (10x10) 8-Bit 24 MHz I/O number 34

February 2012 Doc ID 14733 Rev 12 1/103

STM8S207xx

STM8S208xx

Performance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash,

integrated EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN

Features

■ Core

–Max f

CPU

: up to 24 MHz, 0 wait states @

CPU

≤ 16 MHz

– Advanced STM8 core with Harvard

architecture and 3-stage pipeline

– Extended instruction set

– Max 20 MIPS @ 24 MHz

■ Memories

– Program: up to 128 Kbytes Flash; data

retention 20 years at 55 °C after 10 kcycles

– Data: up to 2 Kbytes true data EEPROM;

endurance 300 kcycles

– RAM: up to 6 Kbytes

■ Clock, reset and supply management

– 2.95 to 5.5 V operating voltage

– Low power crystal resonator oscillator

– External clock input

– Internal, user-trimmable 16 MHz RC

– Internal low power 128 kHz RC

– Clock security system with clock monitor

– Wait, active-halt, & halt low power modes

– Peripheral clocks switched off individually

– Permanently active, low consumption

power-on and power-down reset

■ Interrupt management

– Nested interrupt controller with 32

interrupts

– Up to 37 external interrupts on 6 vectors

■ Timers

– 2x 16-bit general purpose timers, with 2+3

CAPCOM channels (IC, OC or PWM)

– Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-

time insertion and flexible synchronization

– 8-bit basic timer with 8-bit prescaler

– Auto wakeup timer

– Window watchdog, independent watchdog

■ Communications interfaces

– High speed 1 Mbit/s active beCAN 2.0B

– UART with clock output for synchronous

operation - LIN master mode

– UART with LIN 2.1 compliant, master/slave

modes and automatic resynchronization

– SPI interface up to 10 Mbit/s

–I

C interface up to 400 Kbit/s

■ 10-bit ADC with up to 16 channels

■ I/Os

– Up to 68 I/Os on an 80-pin package

including 18 high sink outputs

– Highly robust I/O design, immune against

current injection

– Development support

– Single wire interface module (SWIM) and

debug module (DM)

■ 96-bit unique ID key for each device

Table 1. Device summary

Part numbers: STM8S207xx

STM8S207MB, STM8S207M8, STM8S207RB,

STM8S207R8, STM8S207R6, STM8S207CB,

STM8S207C8, STM8S207C6, STM8S207SB,

STM8S207S8, STM8S207S6, STM8S207K8

STM8S207K6

Part numbers: STM8S208xx

STM8S208MB, STM8S208M8, STM8S208RB,

STM8S208R8, STM8S208R6, STM8S208CB,

STM8S208C8, STM8S208C6, STM8S208SB,

STM8S208S8, STM8S208S6

LQFP80 14x14 LQFP64 10x10

LQFP32 7x7LQFP44 10x10

LQFP64 14x14

LQFP48 7x7

www.st.com

Summary of content (103 pages)

PAGE 1
STM8S207xx STM8S208xx Performance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash, integrated EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN Features ■ Core – Max fCPU: up to 24 MHz, 0 wait states @ fCPU ≤ 16 MHz – Advanced STM8 core with Harvard architecture and 3-stage pipeline – Extended instruction set – Max 20 MIPS @ 24 MHz ■ Memories – Program: up to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles – Data: up to 2 Kbytes true data EEPROM; endurance 300 kcycles – RAM: up to 6
PAGE 2
Contents STM8S207xx, STM8S208xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 6 4.
PAGE 3
STM8S207xx, STM8S208xx 6.2 Contents Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 Electrical characteristics .
PAGE 4
Contents 12 STM8S207xx, STM8S208xx STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.3 12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.2.2 C and assembly toolchains . .
PAGE 5
STM8S207xx, STM8S208xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
PAGE 6
List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. 6/103 STM8S207xx, STM8S208xx ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
STM8S207xx, STM8S208xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
PAGE 8
List of figures Figure 49. 8/103 STM8S207xx, STM8S208xx STM8S207xx/208xx performance line ordering information scheme(1) . . . . . . . . . . . . . . .
PAGE 9
STM8S207xx, STM8S208xx 1 Introduction Introduction This datasheet contains the description of the STM8S20xxx performance line features, pinout, electrical characteristics, mechanical data and ordering information. ● For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016).
PAGE 10
Description 2 STM8S207xx, STM8S208xx Description The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash program memory. They are referred to as high-density devices in the STM8S microcontroller family reference manual. All devices of the STM8S20xxx performance line provide the following benefits: reduced system cost, performance robustness, short development cycles, and product longevity.
PAGE 11
STM8S207xx, STM8S208xx Device Max. number of GPIOs (I/O) Ext. interrupt pins Timer CAPCOM channels Timer complementary outputs A/D converter channels HIgh sink I/Os High density Flash program memory (bytes) Data EEPROM (bytes RAM (bytes) beCAN interface STM8S20xxx performance line features Pin count Table 2.
PAGE 12
Block diagram 3 STM8S207xx, STM8S208xx Block diagram Figure 1. STM8S20xxx performance line block diagram Reset block XTAL 1-24 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR/PDR RC int. 128 kHz BOR Clock to peripherals and core Window WDG STM8 core Independent WDG high density program Flash 400 Kbit/s I2C 10 Mbit/s SPI LIN master SPI emul.
PAGE 13
STM8S207xx, STM8S208xx 4 Product overview Product overview The following section intends to give an overview of the basic features of the STM8S20xxx performance line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance.
PAGE 14
Product overview 4.2 STM8S207xx, STM8S208xx Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.
PAGE 15
STM8S207xx, STM8S208xx Product overview The size of the UBC is programmable through the UBC option byte (Table 13.), in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: ● Main program memory: Up to 128 Kbytes minus UBC ● User-specific boot code (UBC): Configurable up to 128 Kbytes The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area.
PAGE 16
Product overview 4.5 STM8S207xx, STM8S208xx Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features ● Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
PAGE 17
STM8S207xx, STM8S208xx 4.6 Product overview Power management For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. 4.7 ● Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.
PAGE 18
Product overview STM8S207xx, STM8S208xx Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s. 4.8 4.
PAGE 19
STM8S207xx, STM8S208xx 4.12 Table 4.
PAGE 20
Product overview 4.14.
PAGE 21
STM8S207xx, STM8S208xx Product overview Asynchronous communication (UART mode) ● Full duplex communication - NRZ standard format (mark/space) ● Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency ● Separate enable bits for transmitter and receiver ● Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt) ● Transmission error detection with interrupt generation ● Parity control
PAGE 22
Product overview 4.14.4 I2C ● ● 4.14.
PAGE 23
STM8S207xx, STM8S208xx Pinouts and pin description 5 Pinouts and pin description 5.1 Package pinouts LQFP 80-pin pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PI7 PI6 PE0 (HS)/CLK_CCO PE1(T)/I2C_SCL PE2 (T]/I 2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 PI5 PI4 Figure 3.
PAGE 24
Pinouts and pin description LQFP 64-pin pinout PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2[ADC_ETR] PD2 (HS)/TIM3_CH1[TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 Figure 4.
PAGE 25
STM8S207xx, STM8S208xx LQFP 48-pin pinout PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PE3/TIM1_BKIN Figure 5.
PAGE 26
Pinouts and pin description LQFP 44-pin pinout PD7/TLI [TIM1_CH4] PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1[BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA Figure 6.
PAGE 27
STM8S207xx, STM8S208xx LQFP 32-pin pinout PD7/TLI PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1[TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] Figure 7.
PAGE 28
Pinouts and pin description Table 5.
PAGE 29
STM8S207xx, STM8S208xx PP OD - PH3 Speed - High sink LQFP32 - Output Ext. interrupt LQFP44 - floating LQFP48 16 Pin name Type LQFP64 Input LQFP80 Pin number Main function (after reset) Pin description (continued) wpu Table 6.
PAGE 30
Pinouts and pin description Output - PH4/TIM1_ETR I/O X X O1 X X Port H4 36 - - - - PH5/ TIM1_CH3N I/O X X O1 X Timer 1 X Port H5 inverted channel 3 37 - - - - PH6/ TIM1_CH2N I/O X X O1 X Timer 1 X Port H6 inverted channel 2 38 - - - - PH7/ TIM1_CH1N I/O X X O1 X Timer 1 X Port H7 inverted channel 2 - - PE7/AIN8 I/O X X X O1 X X Port E7 Analog input 8 - PE6/AIN9 I/O X X X O1 X X Port E6 Analog input 9 41 33 25 23 17 PE5/SPI_NSS I/O X X X O1 X X SPI Port E5
PAGE 31
STM8S207xx, STM8S208xx Default alternate function I/O X X O1 X X Port G2 55 46 - - - PG3 I/O X X O1 X X Port G3 56 47 - - - PG4 I/O X X O1 X X Port G4 57 48 - - - PI0 I/O X X O1 X X Port I0 58 - - - - PI1 I/O X X O1 X X Port I1 59 - - - - PI2 I/O X X O1 X X Port I2 60 - - - - PI3 I/O X X O1 X X Port I3 61 - - - - PI4 I/O X X O1 X X Port I4 62 - - - - PI5 I/O X X O1 X X Port I5 63 49 - - - PG5 I/O X X O1 X X Port G5 64 5
PAGE 32
Pinouts and pin description PD6/ UART3_RX(1) 80 64 48 44 32 PD7/TLI X Port D6 UART3 data receive I/O X X X O1 X X Port D7 Top level interrupt PP O1 X OD X Speed X floating I/O X Type Ext. interrupt 79 63 47 43 31 Pin name Output wpu Input LQFP32 LQFP44 LQFP48 LQFP64 LQFP80 Pin number Main function (after reset) Pin description (continued) High sink Table 6.
PAGE 33
STM8S207xx, STM8S208xx Memory and register map 6 Memory and register map 6.1 Memory map Figure 8.
PAGE 34
Memory and register map STM8S207xx, STM8S208xx Table 7 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 7. Flash, Data EEPROM and RAM boundary addresses Memory area Flash program memory RAM Data EEPROM 6.
PAGE 35
STM8S207xx, STM8S208xx Table 8.
PAGE 36
Memory and register map Table 9.
PAGE 37
STM8S207xx, STM8S208xx Table 9.
PAGE 38
Memory and register map Table 9.
PAGE 39
STM8S207xx, STM8S208xx Table 9.
PAGE 40
Memory and register map Table 9.
PAGE 41
STM8S207xx, STM8S208xx Table 9.
PAGE 42
Memory and register map Table 9.
PAGE 43
STM8S207xx, STM8S208xx Table 10.
PAGE 44
Memory and register map Table 10. STM8S207xx, STM8S208xx CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register Label Register Name Reset Status DM_CSR1 DM debug module control/status register 1 0x10 DM_CSR2 DM debug module control/status register 2 0x00 DM_ENFCTR DM enable function register 0xFF 0x00 7F98 0x00 7F99 0x00 7F9A DM 0x00 7F9B to 0x00 7F9F Reserved area (5 bytes) 1. Accessible by debug module only 2.
PAGE 45
STM8S207xx, STM8S208xx Interrupt vector mapping 7 Interrupt vector mapping Table 11. Interrupt mapping IRQ no.
PAGE 46
Option bytes 8 STM8S207xx, STM8S208xx Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 12: Option bytes below.
PAGE 47
STM8S207xx, STM8S208xx Table 13. Option bytes Option byte description Option byte no. Description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.
PAGE 48
Option bytes STM8S207xx, STM8S208xx Table 13. Option byte description (continued) Option byte no.
PAGE 49
STM8S207xx, STM8S208xx Table 13. Option bytes Option byte description (continued) Option byte no. OPTBL Description BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details.
PAGE 50
Unique ID 9 STM8S207xx, STM8S208xx Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.
PAGE 51
STM8S207xx, STM8S208xx Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 52
Electrical characteristics 10.1.5 Pin loading conditions 10.1.6 Loading capacitor STM8S207xx, STM8S208xx The loading conditions used for pin parameter measurement are shown in Figure 10. Figure 10. Pin loading conditions STM8 pin 50 pF 10.1.7 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 11.
PAGE 53
STM8S207xx, STM8S208xx 10.2 Electrical characteristics Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 15.
PAGE 54
Electrical characteristics Table 16. STM8S207xx, STM8S208xx Current characteristics Symbol Max.
PAGE 55
STM8S207xx, STM8S208xx 10.3 Electrical characteristics Operating conditions The device must be used in operating conditions that respect the parameters in Table 18. In addition, full account must be taken of all physical capacitor characteristics and tolerances. Table 18.
PAGE 56
Electrical characteristics STM8S207xx, STM8S208xx Figure 12. fCPUmax versus VDD fCPU [MHz] 24 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONALITY GUARANTEED @ TA -40 to 105 °C 16 FUNCTIONALITY GUARANTEED @ TA -40 to 125 °C 12 8 4 0 2.95 4.0 5.0 5.5 SUPPLY VOLTAGE [V] Table 19. Symbol tVDD Operating conditions at power-up/power-down Parameter Conditions Min Typ Max VDD rise time rate 2(1) ∞ VDD fall time rate 2(1) ∞ tTEMP Reset release delay VIT+ Power-on reset threshold 2.
PAGE 57
STM8S207xx, STM8S208xx 10.3.2 Electrical characteristics Supply current characteristics The current consumption is measured as described in Figure 9 on page 51. Total current consumption in run mode The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled (clock stopped by Peripheral Clock Gating registers) except if explicitly mentioned.
PAGE 58
Electrical characteristics Table 21. Symbol STM8S207xx, STM8S208xx Total current consumption with code execution in run mode at VDD = 3.3 V Parameter Conditions IDD(RUN) Supply current in run mode, code executed from Flash 4.0 HSE user ext. clock (24 MHz) 3.7 HSE crystal osc. (16 MHz) 2.9 HSE user ext. clock (16 MHz) 2.7 5.8 HSI RC osc. (16 MHz) 2.5 3.4 HSE user ext. clock (16 MHz) 1.2 4.1 HSI RC osc. (16 MHz) 1.0 1.3 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16MHz/8) 0.
PAGE 59
STM8S207xx, STM8S208xx Electrical characteristics Total current consumption in wait mode Table 22. Symbol Total current consumption in wait mode at VDD = 5 V Parameter Conditions IDD(WFI) Max(1) Unit HSE crystal osc. (24 MHz) 2.4 HSE user ext. clock (24 MHz) 1.8 HSE crystal osc. (16 MHz) 2.0 HSE user ext. clock (16 MHz) 1.4 4.4 HSI RC osc. (16 MHz) 1.2 1.6 mA fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.0 fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8)(2) 0.
PAGE 60
Electrical characteristics STM8S207xx, STM8S208xx Total current consumption in active halt mode Table 24.
PAGE 61
STM8S207xx, STM8S208xx Electrical characteristics Total current consumption in halt mode Table 26. Symbol IDD(H) Table 27. Symbol IDD(H) Total current consumption in halt mode at VDD = 5 V Parameter Supply current in halt mode Conditions Typ Flash in operating mode, HSI clock after wakeup Max at 85 °C Max at 125 °C Unit 63.5 µA Flash in powerdown mode, HSI clock after wakeup 6.5 35 100 Total current consumption in halt mode at VDD = 3.
PAGE 62
Electrical characteristics STM8S207xx, STM8S208xx Total current consumption and timing in forced reset state Table 29. Total current consumption and timing in forced reset state Symbol Parameter Conditions IDD(R) Supply current in reset state tRESETBL Reset release to bootloader vector fetch Typ VDD = 5 V 1.6 VDD = 3.3 V 0.8 Max(1) Unit mA 150 µs 1. Data guaranteed by design, not tested in production.
PAGE 63
STM8S207xx, STM8S208xx Electrical characteristics Current consumption curves Figure 14 and Figure 15 show typical current consumption measured with code executing in RAM. Figure 14. Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz -40˚C 25˚C 4 85˚C 3.5 IDD(RUN)HSI [mA] 125˚C 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 15. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz -40˚C 25˚C 2.5 85˚C 125˚C IDD(WFI)HSI [mA] 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
PAGE 64
Electrical characteristics 10.3.3 STM8S207xx, STM8S208xx External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 31. HSE user external clock characteristics Symbol Parameter Conditions fHSE_ext User external clock source frequency VHSEH(1) OSCIN input pin high level voltage Min Typ Max Unit 0 24 MHz 0.7 x VDD VDD + 0.
PAGE 65
STM8S207xx, STM8S208xx Table 32. Electrical characteristics HSE oscillator characteristics Symbol Parameter Conditions External high speed oscillator frequency fHSE Min 1 Feedback resistor RF C(1) gm Max Unit 24 MHz 220 Recommended load capacitance IDD(HSE) Typ kΩ (2) HSE oscillator power consumption 20 pF C = 20 pF, fOSC = 24 MHz 6 (startup) 2 (stabilized)(3) C = 10 pF, fOSC = 24 MHz 6 (startup) 1.
PAGE 66
Electrical characteristics 10.3.4 STM8S207xx, STM8S208xx Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. fHSE High speed internal RC oscillator (HSI) Table 33.
PAGE 67
STM8S207xx, STM8S208xx Electrical characteristics Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 34. LSI oscillator characteristics Symbol fLSI Parameter Conditions Frequency tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator power consumption Min Typ Max Unit 110 128 146 kHz 7(1) µs 5 µA 1. Guaranteeed by design, not tested in production. Figure 19.
PAGE 68
Electrical characteristics 10.3.5 STM8S207xx, STM8S208xx Memory characteristics RAM and hardware registers Table 35. RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data retention mode(1) Halt mode (or reset) VIT-max(2) V 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. 2. Refer to Table 19 on page 56 for the value of VIT-max.
PAGE 69
STM8S207xx, STM8S208xx 10.3.6 Electrical characteristics I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 37.
PAGE 70
Electrical characteristics STM8S207xx, STM8S208xx Figure 20. Typical VIL and VIH vs VDD @ 4 temperatures -40˚C 6 25˚C 85˚C 5 VIL/VIH [V] 125˚C 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 21. Typical pull-up resistance vs VDD @ 4 temperatures -40˚C 25˚C 60 Pull-up resistance [ΩW] 85˚C 55 125˚C 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 22.
PAGE 71
STM8S207xx, STM8S208xx Table 38. Symbol VOL VOH Electrical characteristics Output driving current (standard ports) Parameter Conditions Min Max Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V 2 Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V 1(1) Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 2.8 Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V 2.1(1) Unit V V 1. Data based on characterization results, not tested in production Table 39.
PAGE 72
Electrical characteristics STM8S207xx, STM8S208xx Typical output level curves Figure 24 to Figure 31 show typical output level curves measured with output on a single pin. Figure 23. Typ. VOL @ VDD = 5 V (standard ports) -40˚C 1.5 25˚C 85˚C 1.25 125˚C VOL [V] 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOL [mA] Figure 24. Typ. VOL @ VDD = 3.3 V (standard ports) -40˚C 1.5 25˚C 85˚C 1.25 125˚C VOL [V] 1 0.75 0.5 VOL [V] 0.25 0 0 1 2 3 4 5 6 7 IOL [mA] Figure 25. Typ.
PAGE 73
STM8S207xx, STM8S208xx Electrical characteristics Figure 26. Typ. VOL @ VDD = 3.3 V (true open drain ports) -40˚C 2 IOL [mA] 25˚C 1.75 85˚C 1.5 125˚C 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 VOL [V] Figure 27. Typ. VOL @ VDD = 5 V (high sink ports) -40˚C 1.5 25˚C 85˚C 1.25 125˚C VOL [V] 1 0.75 0.5 0.25 0 0 5 10 15 20 25 IOL [mA] Figure 28. Typ. VOL @ VDD = 3.3 V (high sink ports) -40˚C 1.5 25˚C 85˚C 1.25 125˚C VOL [V] 1 0.75 0.5 0.
PAGE 74
Electrical characteristics STM8S207xx, STM8S208xx Figure 29. Typ. VDD - VOH @ VDD = 5 V (standard ports) -40˚C 2 VDD - VOH [V] 25˚C 1.75 85˚C 1.5 125˚C 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOL [mA] Figure 30. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) -40˚C 2 VDD - VOH [V] 25˚C 1.75 85˚C 1.5 125˚C 1.25 1 0.75 0.5 0.25 0 0 1 2 3 4 5 6 7 IOL [mA] Figure 31. Typ. VDD - VOH @ VDD = 5 V (high sink ports) -40˚C 2 VDD - VOH [V] 25˚C 1.75 85˚C 1.5 125˚C 1.25 1 0.75 0.
PAGE 75
STM8S207xx, STM8S208xx Electrical characteristics Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) -40˚C 2 VDD - VOH [V] 25˚C 1.75 85˚C 1.5 125˚C 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 IOL [mA] 10.3.7 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 41.
PAGE 76
Electrical characteristics STM8S207xx, STM8S208xx Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures -40˚C 25˚C 60 NRESET pull-up resistance [ΩW] 85˚C 55 125˚C 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 35. Typical NRST pull-up current vs VDD @ 4 temperatures 140 NRESET Pull-Up current [µA] 120 100 80 -40˚C 60 25˚C 40 85˚C 20 125˚C 0 0 1 2 3 VDD [V] 4 5 6 ai15069 The reset network shown in Figure 36 protects the device against parasitic resets.
PAGE 77
STM8S207xx, STM8S208xx Electrical characteristics SPI serial peripheral interface 10.3.8 Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42.
PAGE 78
Electrical characteristics STM8S207xx, STM8S208xx Figure 37. SPI timing diagram - slave mode and CPHA = 0 NSS input tSU(NSS) SCK Input CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN LSB IN B I T1 IN th(SI) ai14134 Figure 38.
PAGE 79
STM8S207xx, STM8S208xx Electrical characteristics Figure 39. SPI timing diagram - master mode(1) High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
PAGE 80
Electrical characteristics 10.3.9 STM8S207xx, STM8S208xx I2C interface characteristics Table 43. I2C characteristics Standard mode I2C Fast mode I2C(1) Symbol Parameter Min(2) Max(2) Min(2) Max(2) Unit tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0(3) 0(4) tr(SDA) tr(SCL) SDA and SCL rise time 1000 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 300 th(STA) START condition hold time 4.
PAGE 81
STM8S207xx, STM8S208xx Electrical characteristics Figure 40. Typical application with I2C bus and timing diagram 6$$ 6$$ 34- 3 XXX 3$! )£# BUS 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU 34! 3$! TF 3$! TR 3$! TH 34! 3#, TW 3#,( TSU 3$! TW 3#,, TR 3#, TH 3$! TF 3#, TSU 34! 34/ 3 4/0 TSU 34/ AI 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.
PAGE 82
Electrical characteristics 10.3.10 STM8S207xx, STM8S208xx 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 44. Symbol fADC ADC characteristics Parameter Conditions Min Typ Max VDDA = 3 to 5.5 V 1 4 VDDA = 4.5 to 5.5 V 1 6 3 5.5 V ADC clock frequency Unit MHz VDDA Analog supply VREF+ Positive reference voltage 2.75(1) VDDA V VREF- Negative reference voltage VSSA 0.
PAGE 83
STM8S207xx, STM8S208xx Table 45. Symbol |ET| |EO| |EG| |ED| |EL| Electrical characteristics ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V Parameter Total unadjusted error Offset error (2) (2) Gain error (2) Differential linearity Integral linearity error (2) error (2) Conditions Typ Max(1) fADC = 2 MHz 1 2.5 fADC = 4 MHz 1.4 3 fADC = 6 MHz 1.6 3.5 fADC = 2 MHz 0.6 2 fADC = 4 MHz 1.1 2.5 fADC = 6 MHz 1.2 2.5 fADC = 2 MHz 0.2 2 fADC = 4 MHz 0.6 2.5 fADC = 6 MHz 0.
PAGE 84
Electrical characteristics STM8S207xx, STM8S208xx Figure 41. ADC accuracy characteristics EG 1023 1022 1021 1LSB IDEAL V –V DDA SSA = ----------------------------------------1024 (2) ET 7 (3) (1) 6 5 EO 4 EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 1021102210231024 VDDA 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
PAGE 85
STM8S207xx, STM8S208xx 10.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
PAGE 86
Electrical characteristics STM8S207xx, STM8S208xx Electromagnetic interference (EMI) Emission tests conform to the SAE IEC 61967-2 standard for test software, board layout and pin loading. Table 48. EMI data Conditions Symbol Max fHSE/fCPU(1) Parameter Monitored frequency band General conditions Peak level SEMI SAE EMI level VDD = 5 V TA = 25 °C LQFP80 package conforming to SAE IEC 61967-2 Unit 8 MHz/ 8 MHz/ 8 MHz/ 8 MHz 16 MHz 24 MHz 0.
PAGE 87
STM8S207xx, STM8S208xx Electrical characteristics Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: ● A supply overvoltage (applied to each power supply pin) ● A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 50.
PAGE 88
Package characteristics 11 STM8S207xx, STM8S208xx Package characteristics To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark.
PAGE 89
STM8S207xx, STM8S208xx Package characteristics 11.1 Package mechanical data 11.1.1 LQFP package mechanical data Figure 43. 80-pin low profile quad flat package (14 x 14) D ccc C D1 A A2 D3 41 60 40 61 b L1 E3 E1 E L A1 K 80 Pin 1 identification Table 51. 1 c 1S_ME 80-pin low profile quad flat package mechanical data inches(1) mm Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.220 c 0.090 D 15.800 D1 13.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.
PAGE 90
Package characteristics STM8S207xx, STM8S208xx Figure 44. 64-pin low profile quad flat package (14 x 14) D ccc C D1 A A2 D3 33 48 32 49 b L1 E3 E1 E L A1 K 64 17 Pin 1 identification Table 52. 16 1 c 1R_ME 64-pin low profile quad flat package mechanical data (14 x 14) inches(1) mm Symbol Min Typ A Max Min 1.600 A1 0.050 A2 1.350 b 0.300 C 0.090 D 15.800 D1 13.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.
PAGE 91
STM8S207xx, STM8S208xx Package characteristics Figure 45. 64-pin low profile quad flat package (10 x 10) D ccc C D1 A A2 D3 33 48 32 49 b L1 E3 E1 E L A1 K 64 17 Pin 1 identification Table 53. 16 1 c 5W_ME 64-pin low profile quad flat package mechanical data (10 x 10) inches(1) mm Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 C 0.090 Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.
PAGE 92
Package characteristics STM8S207xx, STM8S208xx Figure 46. 48-pin low profile quad flat package (7 x 7) D ccc C D1 D3 A A2 25 36 24 37 L1 b E3 E1 E 48 Pin 1 identification 13 1 L A1 K c 12 5B_ME Table 54. 48-pin low profile quad flat package mechanical data inches(1) mm Symbol Min Typ A Max Min 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.200 0.
PAGE 93
STM8S207xx, STM8S208xx Package characteristics Figure 47. 44-pin low profile quad flat package (10 x 10) D ccc C D1 D3 A A2 23 33 22 34 L1 b E3 E1 E 44 Pin 1 identification 12 1 L A1 K c 11 4Y_ME Table 55. 44-pin low profile quad flat package mechanical data inches(1) mm Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 11.800 D1 9.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.
PAGE 94
Package characteristics STM8S207xx, STM8S208xx Figure 48. 32-pin low profile quad flat package (7 x 7) ccc C D D1 D3 24 A A2 17 16 25 L1 b E3 32 9 Pin 1 identification Table 56. E1 E L A1 1 K c 8 32-pin low profile quad flat package mechanical data inches(1) mm Symbol Min Typ A Max Min 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 9.000 9.
PAGE 95
STM8S207xx, STM8S208xx 11.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 18: General operating conditions on page 55.
PAGE 96
Package characteristics 11.2.2 STM8S207xx, STM8S208xx Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 49: STM8S207xx/208xx performance line ordering information scheme(1) on page 99). The following example shows how to calculate the temperature range needed for a given application.
PAGE 97
STM8S207xx, STM8S208xx 12 STM8 development tools STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.
PAGE 98
STM8 development tools 12.2 STM8S207xx, STM8S208xx Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code is available. 12.2.
PAGE 99
STM8S207xx, STM8S208xx 13 Ordering information Ordering information Figure 49.
PAGE 100
Revision history 14 STM8S207xx, STM8S208xx Revision history Table 58. Document revision history Date Revision 23-May-2008 1 Initial release. 05-Jun-2008 2 Added part numbers on page 1 and in Table 2 on page 11. Updated Section 4: Product overview. Updated Section 10: Electrical characteristics. 22-Jun-2008 3 Added part numbers on page 1 and in Table 2 on page 11. 4 Added 32 pin device pinout and ordering information. Updated UBC option description in Table 13 on page 47.
PAGE 101
STM8S207xx, STM8S208xx Table 58. Revision history Document revision history (continued) Date 10-Jul-2009 13-Apr-2010 Revision Changes 8 cont’d Section 10: Electrical characteristics: Added data for TBD values; updated Table 15: Voltage characteristics and Table 18: General operating conditions; updated VCAP specifications in Table 18 and in Section 10.3.
PAGE 102
Revision history STM8S207xx, STM8S208xx Table 58. Document revision history (continued) Date 14-Sep-2010 22-Mar-2011 10-Feb-2012 102/103 Revision Changes 10 Added part number STM8S208M8 to Table 1: Device summary. Updated "reset state" of Table 5: Legend/abbreviations for pinout table. Added footnote 4 to Table 6: Pin description.
PAGE 103
STM8S207xx, STM8S208xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.