Datasheet

UnitFast mode I
2
C
(1)
Standard mode I
2
CParameterSymbol
Max
(2)
Min
(2)
Max
(2)
Min
(2)
μs0.64.0START condition hold timet
h(STA)
μs0.64.7
Repeated START condition
setup time
t
su(STA)
μs0.64.0STOP condition setup timet
su(STO)
μs1.34.7
STOP to START condition time
(bus free)
t
w(STO:STA)
pF400400Capacitive load for each bus lineC
b
(1)
f
MASTER
, must be at least 8 MHz to achieve max fast I
2
C speed (400kHz).
(2)
Data based on standard I
2
C protocol requirement, not tested in production.
(3)
The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time.
(4)
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
Figure 44: Typical application with I
2
C bus and timing diagram
(1)
ai15385b
START
SDA
I²C bus
V
DD
V
DD
STM8S105xx
SDA
SCL
t
f(SDA)
t
r(SDA)
SCL
t
h(STA)
t
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
r(SCL)
t
f(SCL)
t
h(SDA)
START REPEATED
START
t
su(STA)
t
su(STO)
STOP
t
su(STA:STO)
1. Measurement points are made at CMOS levels: 0.3 x V
DD
and 0.7 x V
DD
95/124DocID14771 Rev 12
Electrical characteristicsSTM8S105xx