Datasheet

Figure 40: Recommended reset pin protection
External
reset
circuit
(optional)
0.1 μF
NRST
VDD
RPU
Filter
Internal reset
STM8
SPI serial peripheral interface10.3.9
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, f
MASTER
frequency and V
DD
supply voltage conditions.
t
MASTER
= 1/f
MASTER
.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43: SPI characteristics
UnitMaxMinConditionsParameterSymbol
MHz80Master modeSPI clock
frequency
f
SCK
1
t
c(SCK)
60Slave mode
ns
25Capacitive load: C = 30 pFSPI clock rise
and fall time
t
r(SCK)
t
f(SCK)
ns
4 x
t
MASTER
Slave modeNSS setup timet
su(NSS)
(1)
ns70Slave modeNSS hold timet
h(NSS)
(1)
ns
t
SCK
/2 +
15
t
SCK
/2 -
15
Master modeSCK high and
low time
t
w(SCKH)
(1)
t
w(SCKL)
(1)
ns
5Master modeData input
setup time
t
su(MI)
(1)
t
su(SI)
(1)
ns
5Slave modeData input
setup time
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Electrical characteristicsSTM8S105xx