Datasheet

Description2

The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program

memory, plus integrated true data EEPROM. They are referred to as medium-density devices

in the STM8S microcontroller family reference manual (RM0016).

All devices of the STM8S105xx access line provide the following benefits: reduced system

cost, performance and robustness, short development cycles, and product longevity.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300

kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog,

and brown-out reset.

Device performance is ensured by a 16 MHz CPU clock frequency and enhanced

characteristics which include robust I/O, independent watchdogs (with a separate clock

source), and a clock security system.

Short development cycles are guaranteed due to application scalability across a common

family product architecture with compatible pinout, memory map and and modular peripherals.

Full documentation is offered with a wide choice of development tools.

Product longevity is ensured in the STM8S family thanks to their advanced core which is

made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.

Table 2: STM8S105xx access line features

STM8S105K4STM8S105K6STM8S105S4STM8S105S6STM8S105C4STM8S105C6Device

323244444848Pin count

252534343838Maximum number

of GPIOs

232331313535Ext. Interrupt pins

888899Timer CAPCOM

channels

333333Timer

complementary

outputs

77991010A/D Converter

channels

121215151616High sink I/Os

16K32K16K32K16K32KMedium density

Flash Program

memory (bytes)

102410241024102410241024Data EEPROM

(bytes)

2K2K2K2K2K2KRAM (bytes)

Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I

C, UART,

Window WDG, Independent WDG, ADC

Peripheral set

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DescriptionSTM8S105xx