Datasheet

Unit
Max
(1)
TypConditionsParameterSymbol
mode
(3)
(1)
Data guaranteed by design, not tested in production.
(2)
t
WU(WFI)
= 2 x 1/f
master
+ 7 x 1/f
CPU.
(3)
Measured from interrupt event to interrupt vector fetch.
(4)
Configured by the REGAH bit in the CLK_ICKR register.
(5)
Configured by the AHALT bit in the FLASH_CR1 register.
(6)
Plus 1 LSI clock depending on synchronization.
Total current consumption and timing in forced reset state10.3.2.6
Table 30: Total current consumption and timing in forced reset state
UnitMax
(1)
TypConditionsParameterSymbol
μA
500V
DD
= 5 VSupply current in reset
state
(2)
I
DD(R)
400V
DD
= 3.3 V
μs150
Reset pin release to
vector fetch
t
RESETBL
(1)
Data guaranteed by design, not tested in production.
(2)
Characterized with all I/Os tied to V
SS
.
Current consumption of on-chip peripherals10.3.2.7
Subject to general operating conditions for V
DD
and T
A
.
HSI internal RC/f
CPU
= f
MASTER
= 16 MHz.
Table 31: Peripheral current consumption
UnitTyp.ParameterSymbol
µA
230TIM1 supply current
(1)
I
DD(TIM1)
115TIM2 supply current
(1)
I
DD(TIM2)
69/124DocID14771 Rev 12
Electrical characteristicsSTM8S105xx