Datasheet

[ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate
function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N,
port B0 alternate function = TIM1_CH1N.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description
AFR6
(check only one option)
[ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate
function = I2C_SCL.
[ ] 0: Remapping option inactive. Default alternate functions used.
Refer to pinout description.
AFR7
(check only one option)
[ ] 1: Port D4 alternate function = BEEP.
OPT3 watchdog
[ ] 0: No reset generated on halt if WWDG active.
WWDG_HALT
(check only one option)
[ ] 1: Reset generated on halt if WWDG active.
[ ] 0: WWDG activated by software.
WWDG_HW
(check only one option)
[ ] 1: WWDG activated by hardware.
[ ] 0: IWDG activated by software.
IWDG_HW
(check only one option)
[ ] 1: IWDG activated by hardware.
[ ] 0: LSI clock is not available as CPU clock source.
LSI_EN
(check only one option)
[ ] 1: LSI clock is available as CPU clock source.
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR
register.
HSITRIM
(check only one option)
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR
register.
OPT4 wakeup
[ ] for 16 MHz to 128 kHz prescaler.
PRSC
(check only one option)
[ ] for 8 MHz to 128 kHz prescaler.
[ ] for 4 MHz to 128 kHz prescaler.
[ ] 0: LSI clock source selected for AWU.
CKAWUSEL
(check only one option)
[ ] 1: HSE clock with prescaler selected as clock source
for AWU.
[ ] 0: External crystal connected to OSCIN/OSCOUT.
EXTCLK
(check only one option)
[ ] 1: External clock signal on OSCIN.
DocID14771 Rev 12116/124
STM8S105xxOrdering information