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STM8S105xx

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,

integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C

LQFP48 7x7

LQFP44 10x10

LQFP32 7x7

SDIP32 400 ml

UFQFPN32 5x5

Features

Core

•

16 MHz advanced STM8 core with Harvard

architecture and 3-stage pipeline

•

Extended instruction set

Memories

•

Medium-density Flash/EEPROM:

Program memory up to 32 Kbytes; data

retention 20 years at 55°C after 10 kcycles

Data memory up to 1 Kbytes true data

EEPROM; endurance 300 kcycles

•

RAM: Up to 2 Kbytes

Clock, reset and supply management

•

2.95 V to 5.5 V operating voltage

•

Flexible clock control, 4 master clock sources:

Low power crystal resonator oscillator

External clock input

Internal, user-trimmable 16 MHz RC

Internal low power 128 kHz RC

•

Clock security system with clock monitor

•

Power management:

Low power modes (wait, active-halt, halt)

Switch-off peripheral clocks individually

•

Permanently active, low consumption power-on

and power-down reset

Interrupt management

•

Nested interrupt controller with 32 interrupts

•

Up to 37 external interrupts on 6 vectors

Timers

•

2x 16-bit general purpose timers, with 2+3

CAPCOM channels (IC, OC or PWM)

•

Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-time

insertion and flexible synchronization

•

8-bit basic timer with 8-bit prescaler

•

Auto wake-up timer

•

Window and independent watchdog timers

Communications interfaces

•

UART with clock output for synchronous

operation, Smartcard, IrDA, LIN

•

SPI interface up to 8 Mbit/s

•

C interface up to 400 Kbit/s

Analog-to-digital converter (ADC)

•

10-bit, ±1 LSB ADC with up to 10 multiplexed

channels, scan mode and analog watchdog

I/Os

•

Up to 38 I/Os on a 48-pin package including 16

high sink outputs

•

Highly robust I/O design, immune against current

injection

Development support

•

Embedded single wire interface module (SWIM)

for fast on-chip programming and non intrusive

debugging

Unique ID

•

96-bit unique key for each device

Table 1: Device summary

Part numberReference

STM8S105K4, STM8S105K6, STM8S105S4,

STM8S105S6, STM8S105C4, STM8S105C6

STM8S105xx

1/124

DocID14771 Rev 12

June 2012

www.st.com

Summary of content (124 pages)

PAGE 1
STM8S105xx Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C Interrupt management Nested interrupt controller with 32 interrupts • • Up to 37 external interrupts on 6 vectors LQFP48 7x7 LQFP44 10x10 UFQFPN32 5x5 LQFP32 7x7 insertion and flexible synchronization Core 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline • • Extended instruction set Memories Medium-density Flash/EEPROM: Program memory up to 32 Kbytes; da
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Contents STM8S105xx Contents 1 2 3 4 Introduction ..............................................................................................................8 Description ...............................................................................................................9 Block diagram ........................................................................................................10 Product overview ....................................................................................
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STM8S105xx Contents 10.1.3 Typical curves ....................................................................................55 10.1.4 Typical current consumption ..............................................................55 10.1.5 Loading capacitor ...............................................................................56 10.1.6 Pin input voltage .................................................................................56 10.2 Absolute maximum ratings ...................................
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List of tables STM8S105xx List of tables Table 1. Device summary .........................................................................................................................1 Table 2. STM8S105xx access line features .............................................................................................9 Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14 Table 4. TIM timer features .............................................
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STM8S105xx List of tables Table 48. EMS data ..............................................................................................................................100 Table 49. EMI data ...............................................................................................................................101 Table 50. ESD absolute maximum ratings ...........................................................................................102 Table 51. Electrical sensitivities ................
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List of figures STM8S105xx List of figures Figure 1. STM8S105xx access line block diagram ................................................................................10 Figure 2. Flash memory organisation ....................................................................................................13 Figure 3. LQFP 48-pin pinout .................................................................................................................21 Figure 4. LQFP 44-pin pinout ........................
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STM8S105xx List of figures Figure 48. 44-pin low profile quad flat package ...................................................................................105 Figure 49. 32-pin low profile quad flat package (7 x 7) ........................................................................106 Figure 50. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ..........................................108 Figure 51. 32-lead shrink plastic DIP (400 ml) package ......................................
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Introduction 1 STM8S105xx Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). • information on programming, erasing and protection of the internal Flash memory • For please refer to the STM8S Flash programming manual (PM0051).
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STM8S105xx 2 Description Description The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program memory, plus integrated true data EEPROM. They are referred to as medium-density devices in the STM8S microcontroller family reference manual (RM0016). All devices of the STM8S105xx access line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity.
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Block diagram 3 STM8S105xx Block diagram Figure 1: STM8S105xx access line block diagram Reset block XTAL 1-16 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Debug/SWIM Up to 32 Kbytes program Flash Master/slave autosynchro LIN master SPI emul.
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STM8S105xx 4 Product overview Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance.
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Product overview STM8S105xx SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.
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STM8S105xx Product overview The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.
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Product overview - STM8S105xx 16 MHz high-speed internal RC oscillator (HSI) 128 kHz low-speed internal RC (LSI) clock: After reset, the microcontroller restarts by default with an internal 2 MHz • Startup clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. security system (CSS): This feature can be enabled by software.
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STM8S105xx 4.7 Product overview Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.
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Product overview 4.10 STM8S105xx TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications.
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STM8S105xx Product overview Timer Counter Prescaler size (bits) Counting CAPCOM Complem. Ext. Timer mode channels outputs trigger synchronization/ chaining TIM4 8 Up 4.
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Product overview STM8S105xx • LIN master mode • LIN slave mode Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) • transmit and receive baud rates up to 1 Mbit/s (f /16) and capable of • Programmable following any standard baud rate regardless of the input frequency • Separate enable bits for transmitter and receiver receiver wakeup modes: • TwoAddress bit (MSB) Idle line (interrupt) • Transmission error detection with interrupt generation • Parity contro
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STM8S105xx 4.14.
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Pinout and pin description 5 STM8S105xx Pinout and pin description Table 5: Legend/abbreviations for pinout tables Type I= Input, O = Output, S = Power supply Level Input CM = CMOS Output HS = High sink Output speed O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Port and control configuration Reset state Input float = floating, wpu = weak pull-up Outpu
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STM8S105xx STM8S105 pinouts and pin description NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 (HS) PA4 (HS) PA5 (HS) PA6 PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDAA PE3/TIM1_BKIN PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] Figure 3: LQFP 48-pin pinout 1 48 47 46 45 44 43 42 41 40 39 38 37 36 2 35 3 34 4 33 5 32 6 31
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Pinout and pin description STM8S105xx PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] Figure 4: LQFP 44-pin pinout NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 31 PG1 PG0 PC7 (HS)/SPI_MISO 4 30 PC6 (HS)/SPI_MOSI VSS VCAP VDD VDDIO_1 5 29 6 28 7 27 8 26 (HS) PA4 (HS) PA5
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STM8S105xx Pinout and pin description PD7/TLI [TIM1_CH4] PD6/UART2_RX PD5/UART2_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] Figure 5: LQFP/UFQFPN 32-pin pinout 32 31 30 29 28 27 26 25 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4 1 24 2 23 3 22 4 21 5 20 6 19 18 7 17 8 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/T
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Pinout and pin description STM8S105xx Figure 6: SDIP 32-pin pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ADC_ETR/TIM2_CH2/(HS) PD3 [BEEP] TIM2_CH1/(HS) PD4 UART2_TX/PD5 UART2_RX/PD6 [TIM1_CH4] TLI/PD7 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4 VDDA VSSA [I2C_SDA] AIN5/PB5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 P
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STM8S105xx Pinout and pin description Pin number LQFP48 Pin name Type LQFP44 LQFP32/ SDIP32 - - - Output floating wpu Ext.
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Pinout and pin description Pin number LQFP48 STM8S105xx Pin name Type LQFP44 LQFP32/ SDIP32 Input Output floating wpu Ext.
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STM8S105xx Pinout and pin description Pin number LQFP48 Pin name Type LQFP44 LQFP32/ SDIP32 37 25 30 Output floating wpu Ext.
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Pinout and pin description STM8S105xx Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).
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STM8S105xx Memory and register map 6 Memory and register map 6.1 Memory map Figure 7: Memory map 0x00 0000 RAM (2 Kbytes) 0x00 07FF 512 bytes stack Reserved 0x00 4000 0x00 43FF 0x00 4400 0x00 47FF 0x00 4800 0x00 487F 0x00 4900 1 Kbyte data EEPROM Reserved Option bytes Reserved 0x00 4FFF 0x00 5000 GPIO and periph. reg.
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Memory and register map STM8S105xx Table 7: Flash, Data EEPROM and RAM boundary addresses Memory area Size (bytes) Start address End address Flash program memory 32K 0x00 8000 0x00 FFFF 16K 0x00 8000 0x00 BFFF RAM 2K 0x00 0000 0x00 07FF Data EEPROM 1024 0x00 4000 0x00 43FF 6.2 Register map 6.2.
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STM8S105xx Address Memory and register map Block Register label Register name Reset status 0x00 500A Port C PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xXX 0x00 500C PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F Port D PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX 0x0
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Memory and register map Address 32/124 Block STM8S105xx Register label Register name Reset status 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E Port G PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0xXX 0x00 5020 PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 0x00 5023 Port H PH_ODR Port H data output latch register 0x00 0
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STM8S105xx 6.2.
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Memory and register map STM8S105xx Address Block 0x00 50A2 to 0x00 50B2 Reserved area (17 bytes) 0x00 50B3 RST 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 CLK 0x00 50C1 34/124 Register label Register name Reset status Reset status register 0xXX CLK_ICKR Internal clock control register 0x01 CLK_ECKR External clock control register 0x00 RST_SR 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK (1) CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock m
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STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 50CE to 0x00 50D0 Reserved area (3 bytes) 0x00 50D1 WWDG WWDG_CR WWDG control register 0x7F 0x00 50D2 WWDG_WR WWDR window register 0x7F IWDG_KR IWDG key register 0xXX 0x00 50E1 IWDG_PR IWDG prescaler register 0x00 0x00 50E2 IWDG_RLR IWDG reload register 0xFF 0x00 50D3 to 0x00 50DF Reserved area (13 bytes) 0x00 50E0 IWDG 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 A
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Memory and register map Address STM8S105xx Register label Register name Reset status 0x00 5204 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF 0x00 5208 to Block Reserved area (8 bytes) 0x00 520F 0x00 5210 36/124 2 I C 2 0x00 2 0x00 2 0x00 2 0x00 I2C_CR1 I C control register 1 0x00 5211 I2C_CR2 I C control register 2 0x00 5212 I2C_FREQR I
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STM8S105xx Address Memory and register map Block 0x00 521E 0x00 521F to Register label Register name I2C_PECR I C packet error checking register 0x00 UART2 status register 0xC0 2 Reset status Reserved area (17 bytes) 0x00 522F 0x00 5230 to 0x00 523F Reserved area (6 bytes) 0x00 5240 UART2 UART2_SR 0x00 5241 UART2_DR UART2 data register 0xXX 0x00 5242 UART2_BRR1 UART2 baud rate register 1 0x00 0x00 5243 UART2_BRR2 UART2 baud rate register 2 0x00 0x00 5244 UART2_CR1 UART2 con
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Memory and register map Address STM8S105xx Block Register label Register name Reset status 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/ compare mode 0x00 register 1 0x00 525
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STM8S105xx Address Memory and register map Block Register label Register name 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/ compare register 1 high 0x00 0x00 5266 TIM1_CCR1L TIM1 capture/ compare register 1 low 0x00 0x00 5267 TIM1_CCR2H TIM1 capture/ compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture/ compare r
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Memory and register map Address STM8S105xx Block Register label Register name Reset status 0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture/ compare mode 0x00 register 1 0x00 5306 TIM2_CCMR2 TIM2 capture/ compare mode 0x00 register 2 0x00 5307 TIM2_CCMR3 TIM2 capture/ compare mode 0x00 registe
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STM8S105xx Address Memory and register map Block Register label Register name 0x00 5311 TIM2_CCR2H TIM2 capture/ compare reg.
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Memory and register map Address 42/124 STM8S105xx Block Register label Register name 0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 532D TIM3_CCR1H TIM3 capture/ compare register 1 high 0x00 0x00 532E TIM3_CCR1L TIM3 capture/ compare register 1 low 0x00 0x00 532F TIM3_CCR2H TIM3 capture/ compare register 2 high 0x00 0x00 5330 TIM3_CCR2L TIM3 capture/ compare register 2 low 0x00 TIM4_CR1 TIM4 control register
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STM8S105xx Memory and register map Address Block Register label Register name Reset status 0x00 53F4 to 0x00 53FF Reserved area (12 bytes) 0x00 5400 ADC1 ADC _CSR ADC control/ status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt t
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Memory and register map Address STM8S105xx Block 0x00 540E Register label Register name Reset status ADC _AWCRH ADC analog watchdog control 0x00 register high 0x00 540F ADC_AWCRL ADC analog watchdog control 0x00 register low 0x00 5410 to 0x00 57FF 6.2.3 Reserved area (1008 bytes) (1) Depends on the previous reset source. (2) Write only register.
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STM8S105xx Address Memory and register map Block 0x00 7F0A Register label Register name Reset status CCR Condition code register 0x28 0x00 7F0B to Reserved area (85 bytes) 0x00 7F5F 0x00 7F60 CPU CFG_GCR Global configuration register 0x00 0x00 7F70 ITC ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF 0x00 7F73 ITC_SPR4 Interrupt software priority re
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Memory and register map Address STM8S105xx Block Register label Register name Reset status 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF 0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control register 1 0x00 0x00 7F97 DM_CR2 DM debug module control register 2 0x00 0x00 7F98 DM_CSR1 DM debug module control/status 0x10 register 1 0x00 7F99 DM_CSR2 DM debug modu
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STM8S105xx 7 Interrupt vector mapping Interrupt vector mapping Table 11: Interrupt mapping IRQ no.
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Interrupt vector mapping STM8S105xx IRQ no.
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STM8S105xx 8 Option bytes Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.
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Option bytes Addr. Option name STM8S105xx Option Option bits byte no. 7 NOPT6 0x480C 0x480D Reserved NOPT7 0x480E 0x487E OPT7 Bootloader OPTBL NOPTBL 0x487F 6 5 4 3 2 1 0 Factory default setting Reserved FFh Reserved 00h Reserved FFh BL[7:0] 00h NBL[7:0] FFh Table 13: Option byte description Option byte no.
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STM8S105xx Option byte no.
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Option bytes STM8S105xx Option byte no. Description OPT6 Reserved OPT7 Reserved OPTBL BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details. For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes).
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STM8S105xx Option bytes Option byte no. (1) Description (2) 0: AFR2 remapping option inactive: Default alternate function . 1: Port D0 alternate function = CLK_CCO.Note: AFR2 option has priority over AFR3 if both are activated. AFR1 Alternate function remapping option 1 (2) 0: AFR1 remapping option inactive: Default alternate functions . 1: Port A3 alternate function = TIM3_CH1; port D2 alternate function TIM2_CH3.
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Unique ID 9 STM8S105xx Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.
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STM8S105xx Electrical characteristics 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 10.1.5 STM8S105xx Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure. Figure 9: Pin loading conditions STM8 PIN 50 pF 10.1.6 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. Figure 10: Pin input voltage STM8 PIN VIN 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device.
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STM8S105xx Symbol Electrical characteristics Ratings (2) Input voltage on any other pin |VDDx VDD| Min Max VSS - 0.3 VDD + 0.3 Variations between different power pins 50 |VSSx - VSS| Variations between all the different ground pins VESD Unit Electrostatic discharge voltage mV 50 see Absolute maximum ratings (electrical sensitivity) (1) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply (2) IINJ(PIN) must never be exceeded.
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Electrical characteristics Symbol IINJ(PIN) (4) (5) STM8S105xx (1) Ratings Max. Injected current on NRST pin ±4 Injected current on OSCIN pin ±4 (6) Injected current on any other pin ΣIINJ(PIN) (1) (4) Unit ±4 (6) Total injected current (sum of all I/O and control pins) ±20 Data based on characterization results, not tested in production. (2) All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply.
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STM8S105xx Electrical characteristics Table 19: General operating conditions Symbol Parameter fCPU VDD/ VDD_IO Conditions Min Max Unit Internal CPU clock frequency 0 16 MHz Standard operating voltage 2.95 5.5 V CEXT: capacitance of external capacitor 470 3300 nF 0.
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Electrical characteristics STM8S105xx (2) This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator. (3) To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Thermal characteristics ) with the value for TJmax given in the current table and the value for ΘJA given in Thermal characteristics.
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STM8S105xx 10.3.1 Electrical characteristics VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit the series inductance to less than 15 nH. Figure 12: External capacitor CEXT ESL C ESR RLeak 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.
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Electrical characteristics Symbol Parameter IDD(RUN) STM8S105xx (1) Conditions Typ Max fCPU = fMASTER/128 = HSI RC osc. 15.625 kHz (16 MH3z/8) 0.75 fCPU = fMASTER LSI RC osc. 0.55 = 128 kHz (128 kHz) Supply fCPU = fMASTER current in run = 16 MHz mode, code executed fromFlash HSE crystal osc. Unit 7.7 (16 MHz) HSE user ext. clock 7.0 8.0 7.0 8.0 (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER = 2 MHz HSI RC osc. 1.5 (2) (16 MHz/8) fCPU = fMASTER/128 = HSI RC osc. 125 kHz (16 MHz) 1.
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STM8S105xx Electrical characteristics (1) Symbol Parameter Conditions mode, code executed from RAM Typ Max HSE user ext. clock 2.6 3.2 2.5 3.2 1.6 2.2 1.3 2.0 Unit (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 HSE user ext. clock = 125 kHz (16 MHz) HSI RC osc. (16 MHz) fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8) 0.75 fCPU = fMASTER = 128 kHz LSI RC osc. 0.55 (128 kHz) Supply fCPU = fMASTER = 16 MHz current in run mode, code executed from Flash HSE crystal osc. 7.
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Electrical characteristics STM8S105xx (1) Symbol Parameter Conditions fCPU = fMASTER = 128 kHz Typ Max LSI RC osc. Unit 0.6 (128 kHz) 10.3.2.2 (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Total current consumption in wait mode Table 23: Total current consumption in wait mode at VDD = 5 V Symbol Parameter Conditions IDD(WFI) Supply current in wait mode fCPU = fMASTER = 16 MHz (1) HSE crystal osc.
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STM8S105xx Electrical characteristics Table 24: Total current consumption in wait mode at VDD = 3.3 V (1) Symbol Parameter Conditions Typ Max Unit IDD(WFI) Supply current in wait mode fCPU = fMASTER = 16 HSE crystal osc. MHz (16 MHz) 1.75 mA HSE user ext. clock 1.55 2.0 (16 MHz) HSI RC osc. 1.5 1.9 (16 MHz) 10.3.2.3 fCPU = fMASTER/128 = 125 kHz HSI RC osc. fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. fCPU = fMASTER = 128 kHz LSI RC osc. 1.3 (16 MHz) 0.7 (2) (16 MHz/8) 0.
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Electrical characteristics STM8S105xx Symbol Parameter Conditions Typ (3) Main Flash mode voltage regulator (2) (MVR) Max at 85 (1) °C Max at Unit 125 (1) °C 140 270 350 68 120 220 12 60 150 Clock source (128 kHz) Power-down mode HSE crystal osc. 1030 (16 MHz) LSI RC osc. (128 kHz) Off Operating mode LSI RC osc. (128 kHz) Power-down mode (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register.
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STM8S105xx Electrical characteristics Symbol Parameter Conditions Main Flash (3) voltage mode regulator (2) (MVR) Typ Max Max at Unit at 85 125 (1) (1) °C °C Clock source Power-down HSE crystal mode osc. 630 (16 MHz) Off Operating mode LSI RC osc. (128 kHz) 140 270 350 LSI RC osc. (128 kHz) 66 120 220 10 60 150 Power-down mode 10.3.2.4 (1) Data based on characterization results, not tested in production. (2) Configured by the REGAH bit in the CLK_ICKR register.
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Electrical characteristics STM8S105xx Table 28: Total current consumption in halt mode at VDD = 3.3 V Symbol Parameter Conditions IDD(H) Supply current in halt mode Flash in operating mode, HSI 60 clock after wakeup 90 150 Flash in powerdown mode, HSI clock after wakeup 20 80 (1) 10.3.2.5 Typ Max at Max at Unit (1) 85 °C 125 (1) °C 4.5 µA Data based on characterization results, not tested in production.
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STM8S105xx Symbol Electrical characteristics Parameter Conditions Typ (1) Unit Max (3) mode (1) Data guaranteed by design, not tested in production. (2) tWU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU. (3) Measured from interrupt event to interrupt vector fetch. (4) Configured by the REGAH bit in the CLK_ICKR register. (5) Configured by the AHALT bit in the FLASH_CR1 register. (6) Plus 1 LSI clock depending on synchronization. 10.3.2.
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Electrical characteristics STM8S105xx Symbol Parameter IDD(TIM3) TIM3 timer supply current (1) 90 IDD(TIM4) TIM4 timer supply current (1) 30 IDD(UART2) UART2 supply current IDD(SPI) SPI supply current IDD(I 2 (2) 2 C) IDD(ADC1) Typ. I C supply current Unit 110 (2) 45 (2) 65 (3) ADC1 supply current when converting 955 (1) Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling).
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STM8S105xx Electrical characteristics Figure 14: Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V Figure 15: Typ. IDD(RUN) vs.
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Electrical characteristics STM8S105xx Figure 16: Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz Figure 17: Typ. IDD(WFI) vs.
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STM8S105xx Electrical characteristics Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 32: HSE user external clock characteristics Symbol Parameter fHSE_ext VHSEH (1) VHSEL (1) ILEAK_HSE (1) Conditions Min Max Unit User external clock source frequency 0 16 MHz OSCIN input pin high level voltage 0.7 x VDD VDD + 0.
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Electrical characteristics STM8S105xx Figure 19: HSE external clocksource V HSEH V HSEL External clock source fHSE OSCIN STM8 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components.
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STM8S105xx Electrical characteristics (2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details (3) Data based on characterization results, not tested in production. (4) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached.
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Electrical characteristics STM8S105xx Symbol Parameter Conditions ACCHSI Accuracy of HSI oscillator User-trimmed with CLK_HSITRIMR register for given VDD and TA (1) conditions Accuracy of HSI oscillator (factory calibrated) tsu(HSI) Min (3) Typ Max (2) 1.0 VDD = 5 V, TA = 25°C -1.0 1.0 VDD = 5 V, 25 °C ≤ TA ≤ 85 °C -2.0 2.0 2.95 ≤ VDD≤ 5.5 V,-40 °C ≤ TA ≤ 125 °C -3.0 (3) (3) (2) 1.0 170 (1) Refer to application note. (2) Guaranteed by design, not tested in production.
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STM8S105xx Electrical characteristics Figure 22: Typical HSI accuracy vs VDD @ 4 temperatures Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 35: LSI oscillator characteristics Symbol Parameter Min Typ Max Unit fLSI Frequency 110 128 146 kHz tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator power consumption (1) (1) 7 5 µs µA Guaranteeed by design, not tested in production.
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Electrical characteristics STM8S105xx Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures 10.3.5 Memory characteristics RAM and hardware registers Table 36: RAM and hardware registers Symbol Parameter VRM Data retention mode (1) Conditions Min Unit Halt mode (or reset) VIT-max (2) V (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
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STM8S105xx Electrical characteristics Symbol Parameter (1) Conditions Typ Max Unit Fast programming time for 1 block (128 bytes) 3.0 3.3 ms terase Erase time for 1 block (128 bytes) 3.0 3.
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Electrical characteristics STM8S105xx Symbol Parameter Conditions VIH Input high level voltage Vhys Hysteresis Rpu Pull-up resistor tR, tF Rise and fall Fast I/Os load = 50 pF time(10 % - 90 %) Min Typ 0.7 x VDD (1) Max Unit VDD + 0.
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STM8S105xx Electrical characteristics Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures Figure 25: Typical pull-up resistance vs VDD @ 4 temperatures DocID14771 Rev 12 81/124
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Electrical characteristics STM8S105xx Figure 26: Typical pull-up current vs VDD @ 4 temperatures 1. The pull-up is a pure resistor (slope goes through 0). Table 39: Output driving current (standard ports) Symbol Parameter VOL VOH (1) Conditions Min Max Unit (1) Output low level with four pins IIO = 4 mA, sunk VDD = 3.3 V 1.0 Output low level with eight pins sunk IIO= 10 mA, 2.
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STM8S105xx Electrical characteristics Symbol Parameter (1) Conditions Max IIO = 10 mA, VDD = 5 V 1.0 IIO = 20 mA, VDD = 5 V 2.
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Electrical characteristics STM8S105xx Figure 27: Typ. VOL @ VDD = 5 V (standard ports) Figure 28: Typ. VOL @ VDD = 3.
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STM8S105xx Electrical characteristics Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports) Figure 30: Typ. VOL @ VDD = 3.
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Electrical characteristics STM8S105xx Figure 31: Typ. VOL @ VDD = 5 V (high sink ports) Figure 32: Typ. VOL @ VDD = 3.
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STM8S105xx Electrical characteristics Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports) Figure 34: Typ. VDD - VOH @ VDD = 3.
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Electrical characteristics STM8S105xx Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports) Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 10.3.8 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 42: NRST pin characteristics Symbol Parameter Conditions VIL(NRST) NRST input low Min -0.3 (1) Typ Max - level voltage VIH(NRST) 88/124 NRST input high Unit 0.3 x VDD V IOL=2 mA 0.
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STM8S105xx Symbol Electrical characteristics Parameter Conditions NRST output low Max Unit - - 0.5 30 55 80 - - 75 (1) level voltage RPU(NRST) Typ (1) level voltage VOL(NRST) Min NRST pull-up (2) kΩ resistor tI FP(NRST) NRST input filtered (3) pulse ns tIN FP(NRST) NRST input not (3) 500 - - 15 - - filtered pulse tOP(NRST) NRST output pulse (3) (1) Data based on characterization results, not tested in production.
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Electrical characteristics STM8S105xx Figure 38: Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table 38: I/O static characteristics ), otherwise the reset is not taken into account internally.
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STM8S105xx Electrical characteristics Figure 40: Recommended reset pin protection STM8 VDD RPU External reset circuit NRST Internal reset Filter 0.1 μF (optional) 10.3.9 SPI serial peripheral interface Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER.
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Electrical characteristics Symbol (1) th(MI) th(SI) (1) ta(SO) (1) (2) tdis(SO) tv(SO) tv(MO) th(SO) th(MO) (1) (3) (1) (1) (1) (1) STM8S105xx Parameter Conditions Min Data input hold time Master mode 7 Data input hold time Slave mode 10 Data output access time Slave mode Data output disable time Slave mode Data output valid time Slave mode Data output valid time Master mode Data output hold time Slave mode Max ns ns 3x tMASTER 25 (after enable edge) 36 28 (after en
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STM8S105xx Electrical characteristics Figure 41: SPI timing diagram - slave mode and CPHA = 0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN B I T1 IN LSB IN th(SI) ai14134 (1) Figure 42: SPI timing diagram - slave mode and CPHA = 1 NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO
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Electrical characteristics STM8S105xx (1) Figure 43: SPI timing diagram - master mode High NSS input SCK intput SCK output tc(SCK) CPHA= 0 CPOL=0 CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136b 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 10.3.
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STM8S105xx Symbol Electrical characteristics 2 Parameter Standard mode I C (2) (2) Min th(STA) START condition hold time tsu(STA) Repeated START condition setup time tsu(STO) STOP condition setup time tw(STO:STA) STOP to START condition time (bus free) Cb Max 2 (1) Fast mode I C (2) Unit (2) Min Max 4.0 0.6 μs 4.7 0.6 μs 4.0 0.6 μs 4.7 1.3 μs Capacitive load for each bus line 400 400 (1) fMASTER, must be at least 8 MHz to achieve max fast I C speed (400kHz).
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Electrical characteristics 10.3.11 STM8S105xx 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 45: ADC characteristics Symbol Parameter Conditions fADC ADC clock frequency Min Typ Max Unit VDDA =2.95 to 5.5 V 1.0 4.0 MHz VDDA =4.5 to 5.5 V 1.0 6.0 5.5 V VDDA Analog supply 3.0 VREF+ Positive reference voltage 2.75 VDDA V VREF- Negative reference voltage (1) V SSA 0.
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STM8S105xx Electrical characteristics changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V Symbol Parameter |ET| Total unadjusted error |EO| |EG| |ED| |EL| (1) (2) (2) Offset error (2) Gain error (2) Differential linearity error (2) Integral linearity error (1) Conditions Typ Max Unit fADC = 2 MHz 1.0 2.5 LSB fADC = 4 MHz 1.4 3.0 fADC = 6 MHz 1.
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Electrical characteristics STM8S105xx Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy. Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V Symbol Parameter |ET| Total unadjusted error |EO| |EG| |ED| |EL| (1) (2) (2) Offset error Gain error (2) (2) Differential linearity error (2) Integral linearity error (1) Conditions Typ Max Unit fADC = 2 MHz 1.1 2.
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STM8S105xx Electrical characteristics Figure 45: ADC accuracy characteristics 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one.
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Electrical characteristics STM8S105xx 10.3.12.1 Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.
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STM8S105xx Electrical characteristics Symbol Parameter Conditions Level/ class and VSS pins to induce a functional disturbance (1) Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). 10.3.12.3 Electromagnetic interference (EMI) Emission tests conform to the IEC61967-2 standard for test software, board layout and pin loading.
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Electrical characteristics STM8S105xx 10.3.12.5 Electrostatic discharge (ESD) Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
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STM8S105xx 11 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 11.
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Package information Dim. D1 STM8S105xx inches Min Typ Max Min Typ Max 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 5.500 0.2165 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.500 0.2165 e 0.500 0.0197 L 0.450 L1 0° ccc (1) 0.600 0.750 0.0177 1.000 k 104/124 (1) mm 3.5° 0.0236 0.0295 0.0394 7.0° 0° 3.5° 0.080 Values in inches are converted from mm and rounded to 4 decimal digits DocID14771 Rev 12 7.0° 0.
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STM8S105xx 11.2 Package information 44-pin LQFP package mechanical data Figure 48: 44-pin low profile quad flat package D ccc C D1 D3 A A2 23 33 22 34 L1 b E3 E1 E 44 Pin 1 identification 12 1 L A1 K c 11 4Y_ME Table 53: 44-pin low profile quad flat package mechanical data Dim. (1) mm Min inches Typ A Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 11.800 D1 9.800 D3 E Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.
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Package information STM8S105xx Dim. (1) mm E1 inches Min Typ Max Min Typ Max 9.800 10.000 10.200 0.3858 0.3937 0.4016 E3 8.000 0.3150 e 0.800 0.0315 L 0.450 0.600 L1 0.750 0.0° 0.0295 0.0394 3.5° 7.0° ccc 11.3 0.0236 1.000 k (1) 0.0177 0.0° 3.5° 0.100 7.0° 0.
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STM8S105xx Package information Table 54: 32-pin low profile quad flat package mechanical data Dim. (1) mm Min inches Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 D3 Max 0.0630 0.150 0.0020 1.400 1.450 0.0531 0.0551 0.0571 0.370 0.450 0.0118 0.0146 0.0177 0.200 0.0035 9.000 9.200 0.3465 0.3543 0.3622 7.000 7.200 0.2677 0.2756 0.2835 5.600 0.0059 0.0079 0.2205 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.
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Package information 11.4 STM8S105xx 32-lead UFQFPN package mechanical data Figure 50: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) AOB8_ME 1. Drawing is not to scale. 2. All leads/pads should be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. 4. Dimensions are in millimeters.
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STM8S105xx Package information Dim. (1) mm inches Min Typ Max Min Typ Max D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D2 3.200 3.450 3.700 0.1260 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e 0.500 L 0.300 0.0197 0.400 0.500 ddd (1) 11.5 0.1457 0.0118 0.0157 0.080 0.0197 0.0031 Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information Dim. STM8S105xx (1) mm Min inches Typ Min Typ Max A1 0.508 0.0200 A2 3.048 3.556 4.572 0.1200 0.1400 0.1800 B 0.356 0.457 0.584 0.0140 0.0180 0.0230 B1 0.762 1.016 1.397 0.0300 0.0400 0.0550 C 0.203 0.254 0.356 0.0079 0.0100 0.0140 D 27.430 27.940 28.450 1.0799 1.1000 1.1201 E 9.906 10.410 11.050 0.3900 0.4098 0.4350 E1 7.620 8.890 9.398 0.3000 0.3500 0.3700 e 1.778 0.0700 eA 10.160 0.4000 eB L (1) 110/124 Max 12.
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STM8S105xx 12 Thermal characteristics Thermal characteristics The maximum chip junction temperature (TJ max) must never exceed the values given in Operating conditions The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x ΘJA) Where: TAmax is the maximum ambient temperature in °C • • Θ is the package junction-to-ambient thermal resistance in ° C/W • P is the sum of P and P (P = P + P ) • Ppower.
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Thermal characteristics 12.1 STM8S105xx Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 12.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code. The following example shows how to calculate the temperature range needed for a given application.
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STM8S105xx 13 Ordering information Ordering information Figure 52: STM8S105xx access line ordering information scheme Example: STM8 S 105 K 4 T 6 C TR Product class Family type S = Standard Sub-family type 105 = access line STM8S105x Pin count K = 32 pins S = 44 pins C = 48 pins Program memory size 4 = 16 Kbytes 6 = 32 Kbytes Package type B = SDIP T = LQFP U = UFQFPN Temperature range 3 = -40 °C to 125 °C 6 = -40 °C to 85 °C Package pitch/thickness No character = 0.5 mm C = 0.
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Ordering information STM8S105xx Contact ............................................................................................. Phone no. ............................................................................................. a Reference FASTROM code ............................................................................................. Preferable format for programing code is .Hex (.
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STM8S105xx Ordering information [ ] 1: Set UBC bit1 [ ] 0: Reset [ ] 1: Set UBC bit2 [ ] 0: Reset [ ] 1: Set UBC bit3 [ ] 0: Reset [ ] 1: Set UBC bit4 [ ] 0: Reset [ ] 1: Set UBC bit5 [ ] 0: Reset [ ] 1: Set OPT2 alternate function remapping AFR0 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description. [ ] 1: Port D3 alternate function = ADC_ETR AFR1 (check only one option) [ ] 0: Remapping option inactive.
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Ordering information STM8S105xx [ ] 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_NCC3, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N. AFR6 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL. AFR7 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used.
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STM8S105xx Ordering information OPT5 crystal oscillator stabilization HSECNT (check only one option) [ ] 2048 HSE cycles [ ] 128 HSE cycles [ ] 8 HSE cycles [ ] 0.5 HSE cycles OPT6 is reserved OPT7 is reserved OPTBL bootloader option byte (check only one option) Refer to the UM0560 (STM8L/S bootloader manual) for more details. [ ] Disable (00h) [ ] Enable (55h) Comments: ........................................................................................................... Supply operating range ...
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STM8 development tools 14 STM8S105xx STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 14.
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STM8S105xx 14.2.1 STM8 development tools STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu.
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Revision history 15 STM8S105xx Revision history Table 58: Document revision history Date Revision Changes 05-Jun-2008 1 Initial release. 23-Jun-2008 2 Corrected number of high sink outputs to 9 in I/Os on Features. Updated part numbers in Table 2: STM8S105xx access line features. 12-Aug-2008 3 Updated part numbers in Table 2: STM8S105xx access line features. USART renamed UART1, LINUART renamed UART2. Added Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices.
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STM8S105xx Date Revision history Revision Changes Added Table 5 on page 22 . Updated Auto wakeup counter. Updated pins 25, 30, and 31 in Pinout and pin description. Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices. Added Table 14: Description of alternate function remapping bits [7:0] of OPT2.
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Revision history Date STM8S105xx Revision Changes Added Unique ID Operating conditions: added introductory text; removed low power dissipation condition for TA, replaced "CEXT" by "VCAP", and added ESR and ESL data in table "general operating conditions". Total current consumption in halt mode: replaced max value of IDD(H) at 85 °C from 20 µA to 25 µA for the condition "Flash in powerdown mode, HSI clock after wakeup in the table "total current consumption in halt mode at VDD = 5 V.
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STM8S105xx Date Revision history Revision Changes Updated Figure 44: Typical application with I2C bus and timing diagram (1) . Updated footnote 1 in Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V and Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V . STM8S105 FASTROM microcontroller option list: removed bits 6 and 7 from OPT1 user boot code area (UBC); added "disable" to 00h and "enable" to 55h of OPTBL bootloader option byte.
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STM8S105xx Please Read Carefully Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.