Datasheet

Figure 38: Recommended reset pin protection
External
reset
circuit
(optional)
0.1 μF
NRST
VDD
RPU
Filter
Internal reset
STM8
SPI serial peripheral interface10.3.8
Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, f
MASTER
frequency and V
DD
supply voltage conditions.
t
MASTER
= 1/f
MASTER
.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43: SPI characteristics
UnitMaxMin
Conditions
(1)
ParameterSymbol
MHz80
Master modeSPI clock
frequency
f
SCK
1/
t
c(SCK)
MHz7
(2)
0
SPI clock frequencyf
SCK
1/ t
c(SCK)
f
SCK
1/
t
c(SCK)
ns
25-
Capacitive load: C = 30 pFSPI clock rise and
fall time
t
r(SCK)
t
f(SCK)
-
4 x
t
MASTER
Slave modeNSS setup timet
su(NSS)
(3)
-70Slave modeNSS hold timet
h(NSS)
(3)
t
SCK
/
2 +15
t
SCK
/
2 - 15
Master modeSCK high and low
time
t
w(SCKH)
(3)
t
w(SCKL)
(3)
-5Master modeData input setup
time
t
su(MI)
(3)
t
su(SI)
(3)
-5Slave mode
-7Master modeData input hold
time
t
h(MI)
(3)
t
h(SI)
(3)
-10Slave mode
DocID15441 Rev 982/117
STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics