Datasheet

Reset

status

Reserved area (1008 bytes)0x00 5410 to

0x00 57FF

(1)

Depends on the previous reset source.

(2)

Write only register.

CPU/SWIM/debug module/interrupt controller registers6.2.3

Table 9: CPU/SWIM/debug module/interrupt controller registers

Reset statusRegister nameRegister labelBlockAddress

0x00AccumulatorA

CPU

(1)

0x00 7F00

0x00Program counter extendedPCE0x00 7F01

0x00Program counter highPCH0x00 7F02

0x00Program counter lowPCL0x00 7F03

0x00X index register highXH0x00 7F04

0x00X index register lowXL0x00 7F05

0x00Y index register highYH0x00 7F06

0x00Y index register lowYL0x00 7F07

0x03Stack pointer highSPH0x00 7F08

0xFFStack pointer lowSPL0x00 7F09

0x28Condition code registerCCR0x00 7F0A

Reserved area (85 bytes)

0x00 7F0B to

0x00 7F5F

0x00Global configuration registerCFG_GCRCPU0x00 7F60

0xFFInterrupt software priority register 1ITC_SPR1

ITC

0x00 7F70

0xFFInterrupt software priority register 2ITC_SPR20x00 7F71

0xFFInterrupt software priority register 3ITC_SPR30x00 7F72

0xFFInterrupt software priority register 4ITC_SPR40x00 7F73

0xFFInterrupt software priority register 5ITC_SPR50x00 7F74

DocID15441 Rev 940/117

STM8S103K3 STM8S103F3 STM8S103F2Memory and register map