Datasheet

Reset

status

0x00TIM2 capture/compare register 1 lowTIM2_CCR1L0x00 5312

0x00TIM2 capture/compare reg. 2 highTIM2_CCR2H0x00 5313

0x00TIM2 capture/compare register 2 lowTIM2_CCR2L0x00 5314

0x00TIM2 capture/compare register 3 highTIM2_CCR3H0x00 5315

0x00TIM2 capture/compare register 3 lowTIM2_CCR3L0x00 5316

Reserved area (43 bytes)0x00 5317 to

0x00 533F

0x00TIM4 control register 1TIM4_CR1TIM40x00 5340

Reserved0x00 5341

Reserved0x00 5342

0x00TIM4 interrupt enable registerTIM4_IER0x00 5343

0x00TIM4 status registerTIM4_SR0x00 5344

0x00TIM4 event generation registerTIM4_EGR0x00 5345

0x00TIM4 counterTIM4_CNTR0x00 5346

0x00TIM4 prescaler registerTIM4_PSCR0x00 5347

0xFFTIM4 auto-reload registerTIM4_ARR0x00 5348

Reserved area (153 bytes)0x00 5349 to

0x00 53DF

0x00ADC data buffer registersADC _DBxRADC10x00 53E0 to

0x00 53F3

Reserved area (12 bytes)0x00 53F4 to

0x00 53FF

DocID15441 Rev 938/117

STM8S103K3 STM8S103F3 STM8S103F2Memory and register map