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STM8S103K3 STM8S103F3 STM8S103F2

Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data

EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C

LQFP32 7x7

UFQFPN32 5x5

TSSOP20

UFQFPN20 3x3

SO20W 300 mils

SDIP32 400 mils

Features

Core

•

16 MHz advanced STM8 core with Harvard

architecture and 3-stage pipeline

•

Extended instruction set

Memories

•

Program memory: 8 Kbytes Flash; data retention

20 years at 55 °C after 10 kcycles

•

Data memory: 640 bytes true data EEPROM;

endurance 300 kcycles

•

RAM: 1 Kbytes

Clock, reset and supply management

•

2.95 to 5.5 V operating voltage

•

Flexible clock control, 4 master clock sources:

Low power crystal resonator oscillator

External clock input

Internal, user-trimmable 16 MHz RC

Internal low power 128 kHz RC

•

Clock security system with clock monitor

•

Power management:

Low power modes (wait, active-halt, halt)

Switch-off peripheral clocks individually

•

Permanently active, low consumption power-on

and power-down reset

Interrupt management

•

Nested interrupt controller with 32 interrupts

•

Up to 27 external interrupts on 6 vectors

Timers

•

Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-time

insertion and flexible synchronization

•

16-bit general purpose timer, with 3 CAPCOM

channels (IC, OC or PWM)

•

8-bit basic timer with 8-bit prescaler

•

Auto wake-up timer

•

Window watchdog and independent watchdog

timers

Communications interfaces

•

UART with clock output for synchronous

operation, Smartcard, IrDA, LIN master mode

•

SPI interface up to 8 Mbit/s

•

C interface up to 400 Kbit/s

Analog to digital converter (ADC)

•

10-bit, ±1 LSB ADC with up to 5 multiplexed

channels, scan mode and analog watchdog

I/Os

•

Up to 28 I/Os on a 32-pin package including 21

high sink outputs

•

Highly robust I/O design, immune against current

injection

Development support

•

Embedded single wire interface module (SWIM)

for fast on-chip programming and non intrusive

debugging

Unique ID

•

96-bit unique key for each device

1/117

DocID15441 Rev 9

June 2012

www.st.com

Summary of content (117 pages)

PAGE 1
STM8S103K3 STM8S103F3 STM8S103F2 Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C Interrupt management Nested interrupt controller with 32 interrupts LQFP32 7x7 UFQFPN32 5x5 • • Up to 27 external interrupts on 6 vectors SDIP32 400 mils Timers Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization • TSSOP20 SO20W 300 mils UFQFPN20 3x3 Features Core 16 MHz advanced STM8 core
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Contents STM8S103K3 STM8S103F3 STM8S103F2 Contents 1 2 3 4 Introduction ..............................................................................................................8 Description ...............................................................................................................9 Block diagram ........................................................................................................10 Product overview ..............................................................
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STM8S103K3 STM8S103F3 STM8S103F2 Contents 9 Unique ID ................................................................................................................49 10 Electrical characteristics ....................................................................................50 10.1 Parameter conditions .................................................................................................50 10.1.1 Minimum and maximum values .........................................................50 10.
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List of tables STM8S103K3 STM8S103F3 STM8S103F2 List of tables Table 1. STM8S103xx access line features .............................................................................................9 Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14 Table 3. TIM timer features ....................................................................................................................16 Table 4. Legend/abbreviations for pinout tables ...
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STM8S103K3 STM8S103F3 STM8S103F2 List of tables Table 48. EMS data ................................................................................................................................91 Table 49. EMI data .................................................................................................................................91 Table 50. ESD absolute maximum ratings .............................................................................................92 Table 51.
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List of figures STM8S103K3 STM8S103F3 STM8S103F2 List of figures Figure 1. Block diagram .........................................................................................................................10 Figure 2. Flash memory organization ....................................................................................................13 Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................20 Figure 4.
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STM8S103K3 STM8S103F3 STM8S103F2 List of figures Figure 48. 32-lead shrink plastic DIP (400 ml) package ........................................................................98 Figure 49. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................101 Figure 50. 20-lead, plastic small outline (300 mils) package ...............................................................101 Figure 51. Recommended footprint for on-board emulation ...............
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Introduction 1 STM8S103K3 STM8S103F3 STM8S103F2 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016).
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STM8S103K3 STM8S103F3 STM8S103F2 2 Description Description The STM8S103x access line 8-bit microcontrollers offer 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost.
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Block diagram 3 STM8S103K3 STM8S103F3 STM8S103F2 Block diagram Figure 1: Block diagram Reset block XTAL 1-16 MHz Clock controller Reset Reset RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Single wire debug interf. 8 Kbytes program Flash Debug/SWIM 400 Kbit/s 8 Mbit/s LIN master SPI emul.
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STM8S103K3 STM8S103F3 STM8S103F2 4 Product overview Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance.
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Product overview STM8S103K3 STM8S103F3 STM8S103F2 SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.
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STM8S103K3 STM8S103F3 STM8S103F2 Product overview program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.
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Product overview - STM8S103K3 STM8S103F3 STM8S103F2 Up to 16 MHz high-speed user-external clock (HSE user-ext) 16 MHz high-speed internal RC oscillator (HSI) 128 kHz low-speed internal RC (LSI) clock: After reset, the microcontroller restarts by default with an internal 2 MHz • Startup clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. security system (CSS): This feature can be enabled by software.
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STM8S103K3 STM8S103F3 STM8S103F2 Product overview Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.
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Product overview STM8S103K3 STM8S103F3 STM8S103F2 • Break input to force the timer outputs into a defined state • Three complementary outputs with adjustable dead time • Encoder mode • Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break 4.
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STM8S103K3 STM8S103F3 STM8S103F2 Product overview • Analog watchdog capability with programmable upper and lower thresholds • Analog watchdog interrupt • External trigger input • Trigger from TIM1 TRGO • End of conversion (EOC) interrupt 4.14 Communication interfaces The following communication interfaces are implemented: UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA mode, single wire mode, LIN2.
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Product overview STM8S103K3 STM8S103F3 STM8S103F2 LIN master mode Emission: Generates 13-bit synch break frame • • Reception: Detects 11-bit break frame 4.14.2 SPI • Maximum speed: 8 Mbit/s (f /2) both for master and slave • Full duplex synchronous transfers • Simplex synchronous transfers on two lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • CRC calculation • 1 byte Tx and Rx buffer • Slave/master selection input pin MASTER 4.14.
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STM8S103K3 STM8S103F3 STM8S103F2 5 Pinout and pin description Pinout and pin description Table 4: Legend/abbreviations for pinout tables Type I= Input, O = Output, S = Power supply Level Input CM = CMOS Output HS = High sink Output speed O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset Port and control configuration Reset state Input float = floating, wpu
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Pinout and pin description 5.
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STM8S103K3 STM8S103F3 STM8S103F2 Pinout and pin description Figure 4: STM8S103Kx SDIP32 pinout [TIM2_CH2] ADC_ETR/(HS) PD3 BEEP/TIM2_CH1/(HS) PD4 UART1_TX(/HS) PD5 UART1_RX/(HS) PD6 [TIM1_CH4] TLI/(HS) PD7 NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD [SPI_NSS] TIM2_CH3/(HS) PA3 PF4 PB7 PB6 I2C_SDA/(T) PB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PD2 (HS) [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM1_BKIN [CLK_CCO] PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC
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Pinout and pin description SDIP 32 LQFP/ UFQFP 32 STM8S103K3 STM8S103F3 STM8S103F2 Input Pin name Output Type Main function Default alternate (after function Ext.
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STM8S103K3 STM8S103F3 STM8S103F2 SDIP 32 LQFP/ UFQFP 32 Input Pin name Pinout and pin description Output Type Main function Default alternate (after function Ext.
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Pinout and pin description STM8S103K3 STM8S103F3 STM8S103F2 5.2 STM8S103Fx TSSOP20/SO20/UFQFPN20 pinout and pin description 5.2.
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STM8S103K3 STM8S103F3 STM8S103F2 5.2.
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Pinout and pin description STM8S103K3 STM8S103F3 STM8S103F2 Pin no. Input Pin name Output Type TSSOP/SO20 UFQFPN20 floating wpu 3 20 PD6/ AIN6/ UART1 _RX I/O 4 1 NRST I/O 5 2 PA1/ OSCIN 6 3 7 (2) X X Ext. interr.
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STM8S103K3 STM8S103F3 STM8S103F2 5.3 Pinout and pin description Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.
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Memory and register map STM8S103K3 STM8S103F3 STM8S103F2 6 Memory and register map 6.1 Memory map Figure 7: Memory map 0x00 0000 RAM (1 Kbyte) 0x00 03FF 0x00 0800 513 bytes stack Reserved 0x00 3FFF 0x00 4000 0x00 427F 0x00 4280 0x00 47FF 0x00 4800 0x00 480A 0x00 480B 0x00 4864 0x00 4865 0x00 4870 0x00 4871 0x00 4FFF 0x00 5000 640 bytes data EEPROM Reserved Option bytes Reserved Unique ID Reserved GPIO and periph. reg.
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STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map 6.2 Register map 6.2.
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Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Reset status Register label Register name PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register PF_DDR Port F data direction register 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 5018 Port E Port F 0x00 501B (1) 0xXX (1) Depends on the external circuitry.
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STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map Address Block Register label Register name 0x00 5062 Flash FLASH _PUKR Flash program memory unprotection 0x00 register 0x00 5063 Reserved area (1 byte) 0x00 5064 Flash 0x00 5065 to 0x00 509F Reserved area (59 bytes) 0x00 50A0 ITC FLASH _DUKR Reset status Data EEPROM unprotection register 0x00 EXTI_CR1 External interrupt control register 1 0x00 EXTI_CR2 External interrupt control register 2 0x00 Reset status register 0xXX C
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Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name Reset status 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD CLK_SWIMCCR SWIM clock control register 0bXXXX XXX0 WWDG_CR WWDG control register 0x7F WWDG_WR WWDR window register 0x7F IWDG_KR IWDG key register 0xXX 0x00 50E1 IWDG
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STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map Address Block Register label Register name Reset status 0x00 50F4 to 0x00 50FF Reserved area (12 bytes) 0x00 5200 SPI SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 5204 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CR
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Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name 0x00 5218 I2C_SR2 I C status register 2 0x00 5219 I2C_SR3 I C status register 3 0x00 521A I2C_ITR I C interrupt control register 0x00 521B I2C_CCRL I C Clock control register low 0x00 521C I2C_CCRH I C Clock control register high 0x00 521D I2C_TRISER I C TRISE register 0x00 521E I2C_PECR Reset status 2 0x00 2 0x0X 2 0x00 2 0x00 2 0x00 2 0x02 I C packet error checking reg
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STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map Address Block Register label Register name Reset status 0x00 523B to 0x00 523F Reserved area (21 bytes) 0x00 5250 TIM1 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0
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Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name Reset status 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture/compare regi
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STM8S103K3 STM8S103F3 STM8S103F2 Address Block Memory and register map Register label Register name Reset status 0x00 5301 Reserved 0x00 5302 Reserved 0x00 5303 TIM2_IER TIM2 Interrupt enable register 0x00 0x00 5304 TIM2_SR1 TIM2 status register 1 0x00 0x00 5305 TIM2_SR2 TIM2 status register 2 0x00 0x00 5306 TIM2_EGR TIM2 event generation register 0x00 0x00 5307 TIM2_CCMR1 TIM2 capture/compare mode register 0x00 1 0x00 5308 TIM2_CCMR2 TIM2 capture/compare mode register 0x00 2
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Memory and register map Address Block STM8S103K3 STM8S103F3 STM8S103F2 Register label Register name 0x00 5312 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5313 TIM2_CCR2H TIM2 capture/compare reg.
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STM8S103K3 STM8S103F3 STM8S103F2 Memory and register map Address Block Register label Register name Reset status 0x00 5400 ADC1 ADC _CSR ADC control/status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable register 0x00
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Memory and register map STM8S103K3 STM8S103F3 STM8S103F2 Address Block Register label 0x00 5410 to 0x00 57FF Reserved area (1008 bytes) Register name Reset status (1) Depends on the previous reset source. (2) Write only register. 6.2.
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STM8S103K3 STM8S103F3 STM8S103F2 Address Block Memory and register map Register label Register name Reset status 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF 0x00 7F78 to 0x00 7F79 0x00 7F80 Reserved area (2 bytes) SWIM SWIM_CSR 0x00 7F81 to 0x00 7F8F SWIM control status register 0x00 Reserved area (15 bytes) 0x00 7F90 DM_BK1RE DM breakpo
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Interrupt vector mapping 7 STM8S103K3 STM8S103F3 STM8S103F2 Interrupt vector mapping Table 10: Interrupt mapping IRQ Source no.
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STM8S103K3 STM8S103F3 STM8S103F2 Interrupt vector mapping IRQ Source no.
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Option bytes 8 STM8S103K3 STM8S103F3 STM8S103F2 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.
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STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. Option bytes Description Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. OPT1 UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Page 0 defined as UBC, memory write-protected 0x02: Pages 0 to 1 defined as UBC, memory write-protected. Page 0 and 1 contain the interrupt vectors. ...
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Option bytes STM8S103K3 STM8S103F3 STM8S103F2 Option byte no.
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STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. Option bytes (1) Description 1: Port D0 alternate function = CLK_CCO. AFR[4:2] Alternate function remapping options 4:2 Reserved. AFR1 Alternate function remapping option 1 (2) 0: AFR1 remapping option inactive: Default alternate functions . 1: Port A3 alternate function = SPI_NSS; port D2 alternate function = TIM2_CH3. AFR0 Alternate function remapping option 0 Reserved. (1) Do not use more than one remapping option in the same port.
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Option bytes STM8S103K3 STM8S103F3 STM8S103F2 Option byte no. Description Reserved (2) AFR1 Alternate function remapping option 1 0: AFR1 remapping option inactive: Default alternate (1) functions . 1: Port A3 alternate function = SPI_NSS; port D2 alternate function = TIM2_CH3. (2) AFR0 Alternate function remapping option 0 0: AFR0 remapping option inactive: Default alternate (1) functions .
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STM8S103K3 STM8S103F3 STM8S103F2 9 Unique ID Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.
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STM8S103K3 STM8S103F3 STM8S103F2 10.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. Figure 9: Pin input voltage STM8 PIN VIN 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Table 17: Current characteristics Symbol Ratings IVDD (1) Max (2) 100 (2) Total current into VDD power lines (source) IVSS Total current out of VSS ground lines (sink) 80 IIO Output current sunk by any I/O and control pin 20 IINJ(PIN) Output current source by any I/Os and control pin - 20 Injected current on NRST pin ±4 Injected current on OSCIN pin ±4 mA (3) (4) (5) ±4 Injected current on any other pin ΣI INJ(PIN) Unit
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STM8S103K3 STM8S103F3 STM8S103F2 10.3 Electrical characteristics Operating conditions Table 19: General operating conditions Symbol Parameter fCPU Internal CPU clock frequency VDD Standard operating voltage (1) VCAP Conditions Min Max 0 16 MHz 2.95 5.5 V 470 3300 nF - 0.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 (1) Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. (2) This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 11: External capacitor CEXT C ESL ESR RLeak 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 10.3.2 Supply current characteristics The current consumption is measured as described in Pin input voltage. 10.3.2.
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Electrical characteristics Symbol Parameter STM8S103K3 STM8S103F3 STM8S103F2 Conditions Typ fCPU = fMASTER = (2) 2 MHz IDD(RUN) fCPU = fMASTER/128 = Supply current 125 kHz in run mode, code executed f CPU = fMASTER/128 = from Flash 15.625 kHz fCPU = fMASTER = 128 kHz (1) Max HSI RC osc. (16 MHz/8) 0.84 1.05 HSI RC osc. (16 MHz) 0.72 0.9 Unit mA HSI RC osc. (16 MHz/8) 0.46 0.58 LSI RC osc. (128 kHz) 0.42 0.57 (1) Data based on characterization results, not tested in production.
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STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Electrical characteristics Conditions Typ (1) Max Unit 128 = 125 kHz fCPU = fMASTER/ 128 = 15.625 kHz fCPU = fMASTER = 128 kHz HSI RC osc. (16 MHz/8) 0.46 0.58 LSI RC osc. (128 kHz) 0.42 0.57 (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 10.3.2.
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Electrical characteristics Symbol Parameter STM8S103K3 STM8S103F3 STM8S103F2 Conditions Typ Max (1) Unit HSE user ext. clock (16 MHz) 1.1 1.3 0.89 1.1 0.7 0.88 0.45 0.57 0.4 0.54 HSI RC osc. (16 MHz) fCPU = fMASTER/ 128 = HSI RC osc. 125 kHz (16 MHz) fCPU = fMASTER/ 128 = HSI RC osc. (2) 15.625 kHz (16 MHz/8) fCPU = fMASTER= LSI RC osc. 128 kHz (128 kHz) (1) Data based on characterization results, not tested in production.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Conditions Symbol Parameter Main voltage regulator (2) (MVR) Supply current IDD(AH) in active halt mode (3) Flash mode Max Max at 85 at 125 Unit °C °C Typ Clock source (1) (1) LSI RC osc. Operating mode (128 kHz) 66 85 110 10 20 40 Off IDD(AH) Supply current in active halt mode LSI RC osc.
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Electrical characteristics 10.3.2.4 STM8S103K3 STM8S103F3 STM8S103F2 Total current consumption in halt mode Table 27: Total current consumption in halt mode at VDD = 5 V Symbol Parameter Conditions Supply current in halt mode Flash in operating mode, HSI clock after wakeup IDD(H) (1) Typ Max at (1) 85 °C 63 Max at (1) Unit 125 °C 75 105 μA Flash in power-down mode, HSI clock after wakeup 6.
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STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Conditions Wakeup time active MVR voltage halt mode to run regulator (3) (4) Typ Flash in operating (5) mode Wakeup time active MVR voltage Flash in HSI halt mode to run regulator (after power-down (5) off Wakeup time from Flash in operating mode mode (6) - (6) - 48 50 wakeup) (5) halt mode to run (3) Unit wakeup) mode mode (5) Flash in power-down mode (1) Data guaranteed by design, not tested in production.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V Table 31: Peripheral current consumption Symbol Parameter Typ.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 12: Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz Figure 13: Typ IDD(RUN) vs.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 14: Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz Figure 15: Typ IDD(WFI) vs.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 16: Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V Figure 17: Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz 10.3.3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for VDD and TA. Table 32: HSE user external clock characteristics Symbol Parameter fHSE_ext User external clock source frequency 0 16 OSCIN input pin high level voltage 0.7 x VDD VDD + 0.
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Electrical characteristics (1) STM8S103K3 STM8S103F3 STM8S103F2 Data based on characterization results, not tested in production. Figure 18: HSE external clocksource V HSEH V HSEL External clock source fHSE OSCIN STM8 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components.
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STM8S103K3 STM8S103F3 STM8S103F2 (1) Electrical characteristics C is approximately equivalent to 2 x crystal Cload. (2) The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details (3) Data based on characterization results, not tested in production. (4) tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is reached.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter ACCHSI Accuracy of HSI User-trimmed with oscillator Conditions Min Typ Max CLK_HSITRIMR register for Unit (3) 1.0 - - Accuracy of HSI VDD = 5 V, TA = 25°C -1.0 - 1.0 oscillator (factory V = 5 V, 25 °C ≤ DD calibrated) T ≤ 85 °C -2.0 - 2.0 given VDD and TA (1) conditions (2) % A 2.95 ≤ VDD≤ 5.5 V,-40 °C ≤ TA ≤ 125 °C tsu(HSI) (2) (2) -3.0 - 3.0 - - 1.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 20: Typical HSI frequency variation vs VDD @ 4 temperatures Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA.
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Electrical characteristics 10.3.5 STM8S103K3 STM8S103F3 STM8S103F2 Memory characteristics RAM and hardware registers Table 36: RAM and hardware registers Symbol Parameter VRM Data retention mode (1) Conditions Min Unit Halt mode (or reset) VIT-max (2) V (1) Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Symbol Parameter Conditions Typ Max 1 - - - 2 - (1) Min Unit Data retention (data memory) after 300k erase/write cycles at TRET = 85°C TA = +125 °C IDD Supply current (Flash programming or erasing mA for 1 to 128 bytes) (1) Data based on characterization results, not tested in production.
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Electrical characteristics Symbol STM8S103K3 STM8S103F3 STM8S103F2 Parameter Conditions Min Typ Max Unit - - 50 (3) (2) Load = 20 pF Standard and high sink I/Os Load = 20 pF Ilkg Digital input leakage current VSS ≤ VIN ≤VDD - - ±1 Ilkg ana Analog input leakage current VSS ≤ VIN ≤ VDD - - ±250 - - ±1 Ilkg(inj) Leakage current in adjacent I/O Injection current ±4 mA (1) (2) (2) μA nA μA Hysteresis voltage between Schmitt trigger switching levels.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 23: Typical pull-up resistance vs VDD @ 4 temperatures Figure 24: Typical pull-up current vs VDD @ 4 temperatures Table 39: Output driving current (standard ports) Symbol Parameter Conditions Output low level with 8 pins sunk IIO= 10 mA, VDD = 5 V VOL Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V VOH Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V DocID15441 Rev 9 Min Max - 2.0 - 2.8 (1) 1.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Conditions Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V (1) Min Max (1) 2.1 Unit - Data based on characterization results, not tested in production Table 40: Output driving current (true open drain ports) Symbol (1) Parameter Conditions Max VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 5 V VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 3.3 V 1.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 25: Typ. VOL @ VDD = 5 V (standard ports) Figure 26: Typ. VOL @ VDD = 3.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 27: Typ. VOL @ VDD = 5 V (true open drain ports) Figure 28: Typ. VOL @ VDD = 3.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 29: Typ. VOL @ VDD = 5 V (high sink ports) Figure 30: Typ. VOL @ VDD = 3.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 31: Typ. VDD - VOH@ VDD = 5 V (standard ports) Figure 32: Typ. VDD - VOH @ VDD = 3.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 33: Typ. VDD - VOH@ VDD = 5 V (high sink ports) Figure 34: Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) 10.3.7 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 42: NRST pin characteristics Symbol Parameter Conditions VIL(NRST) NRST input low (1) Min -0.3 level voltage DocID15441 Rev 9 Typ Max - 0.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter Conditions VIH(NRST) NRST input high (1) level voltage VOL(NRST) IOL=2 mA Typ (2) Unit - VDD + 0.3 - - 0.5 30 55 80 - - 75 (1) NRST pull-up Max 0.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Figure 36: Typical NRST pull-up resistance vs VDD @ 4 temperatures Figure 37: Typical NRST pull-up current vs VDD @ 4 temperatures The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table 38: I/O static characteristics ), otherwise the reset is not taken into account internally.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 38: Recommended reset pin protection STM8 VDD RPU External reset circuit NRST Internal reset Filter 0.1 μF (optional) 10.3.8 SPI serial peripheral interface Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER.
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STM8S103K3 STM8S103F3 STM8S103F2 Symbol ta(SO) (3) (4) Electrical characteristics Parameter (1) Conditions Data output (3) (5) Data output (3) th(SO) th(MO) (3) (3) (3) tMASTER Slave mode 25 Data output valid Slave mode time tv(MO) Unit 3x - disable time tv(SO) Max Slave mode access time tdis(SO) Min (after enable edge) - - (2) 65 Data output valid Master mode time (after enable edge) Data output hold Slave mode time (after enable edge) Data output hold Master mode ti
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Figure 39: SPI timing diagram - slave mode and CPHA = 0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT M SB IN B I T1 IN LSB IN th(SI) ai14134 Figure 40: SPI timing diagram - slave mode and CPHA = 1 NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics (1) Figure 41: SPI timing diagram - master mode High NSS input SCK intput SCK output tc(SCK) CPHA= 0 CPOL=0 CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136b 1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD. 10.3.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Symbol Parameter 2 (2) STOP condition setup time tw(STO:STA) STOP to START condition time (bus free) Cb Fast mode I C (2) Min tsu(STO) 2 (1) Standard mode I C Max (2) Max Min Unit (2) 4.0 - 0.6 - 4.7 - 1.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Table 45: ADC characteristics Symbol Parameter Conditions fADC VDD =2.95 to 5.5 V ADC clock frequency Min Typ Max Unit - 1 4 MHz VDD =4.5 to 5.5 V VAIN (1) Conversion voltage range CADC Internal sample and hold capacitor tS (1) Minimum sampling time fADC = 4 MHz 1 - 6 VSS - VDD V - 3 - pF - 0.
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Electrical characteristics Symbol |EG| |ED| |EL| (1) STM8S103K3 STM8S103F3 STM8S103F2 Parameter (2) Gain error (2) Differential linearity error (2) Integral linearity error (1) Conditions Typ Max fADC = 4 MHz 1.5 3 fADC = 6 MHz 1.8 3 fADC = 2 MHz 1.5 3 fADC = 4 MHz 2.1 3 fADC = 6 MHz 2.2 4 fADC = 2 MHz 0.7 1.5 fADC = 4 MHz 0.7 1.5 fADC = 6 MHz 0.7 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.8 2 fADC = 6 MHz 0.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Symbol Parameter |EG| |ED| |EL| (1) (2) Gain error (2) Differential linearity error (2) Integral linearity error (1) Conditions Typ Max fADC = 4 MHz 1.5 2.5 fADC = 2 MHz 1.3 3 fADC = 4 MHz 2 3 fADC = 2 MHz 0.7 1 fADC = 4 MHz 0.7 1.5 fADC = 2 MHz 0.6 1.5 fADC = 4 MHz 0.8 2 Unit Data based on characterization results, not tested in production. (2) ADC accuracy vs.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
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STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring.
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Electrical characteristics STM8S103K3 STM8S103F3 STM8S103F2 Conditions Symbol Parameter Max fHSE/fCPU General conditions (1) Monitored frequency band 16 MHz/ 16 MHz/ Conforming to 130 MHz SAE IEC 61967-2 130 MHz to 8 MHz 16 MHz 5 5 2.5 2.5 Unit 1 GHz SAE EMI level (1) SAE EMI level Data based on characterisation results, not tested in production. 10.3.11.
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STM8S103K3 STM8S103F3 STM8S103F2 (1) Electrical characteristics Data based on characterization results, not tested in production 10.3.11.6 Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: A supply overvoltage (applied to each power supply pin) • injection (applied to each input, output and configurable I/O pin) are performed • Aoncurrent each sample. This test conforms to the EIA/JESD 78 IC latch-up standard.
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Package information 11 STM8S103K3 STM8S103F3 STM8S103F2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 11.
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STM8S103K3 STM8S103F3 STM8S103F2 Dim. Package information (1) mm Min D3 inches Typ Max Min 5.600 Typ Max 0.2205 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.600 0.2205 e 0.800 0.0315 L 0.450 L1 0.750 0.0177 1.000 k 0.0° ccc (1) 0.600 3.5° 0.0236 0.0295 0.0394 7.0° 0.0° 3.5° 0.100 7.0° 0.
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Package information 11.2 STM8S103K3 STM8S103F3 STM8S103F2 32-lead UFQFPN package mechanical data Figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) AOB8_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. 4. Dimensions are in millimeters.
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STM8S103K3 STM8S103F3 STM8S103F2 Dim. Package information (1) mm inches Min Typ Max Min Typ Max b 0.180 0.250 0.300 0.0071 0.0098 0.0118 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D2 3.200 3.450 3.700 0.1260 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E2 3.200 3.450 3.700 0.1260 0.1358 0.1457 e 0.500 L 0.300 0.0197 0.400 0.500 ddd (1) 11.3 0.1457 0.0118 0.0157 0.080 0.0197 0.0031 Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information STM8S103K3 STM8S103F3 STM8S103F2 1. Drawing is not to scale. Table 54: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data Dim. Min inches Typ Max Min Typ Max D 3.000 0.1181 E 3.000 0.1181 A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 0.152 0.0060 e 0.500 0.0197 L1 0.500 0.550 0.600 0.0197 0.0217 0.0236 L2 0.300 0.350 0.400 0.0118 0.0138 0.0157 L3 0.150 0.
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STM8S103K3 STM8S103F3 STM8S103F2 Dim. Package information (1) mm Min inches Typ Max Min Typ Max A2 3.048 3.556 4.572 0.1200 0.1400 0.1800 B 0.356 0.457 0.584 0.0140 0.0180 0.0230 B1 0.762 1.016 1.397 0.0300 0.0400 0.0550 C 0.203 0.254 0.356 0.0079 0.0100 0.0140 D 27.430 27.940 28.450 1.0799 1.1000 1.1201 E 9.906 10.410 11.050 0.3900 0.4098 0.4350 E1 7.620 8.890 9.398 0.3000 0.3500 0.3700 e 1.778 0.0700 eA 10.160 0.4000 eB L (1) 12.700 2.
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Package information 11.5 STM8S103K3 STM8S103F3 STM8S103F2 20-pin TSSOP package mechanical data Figure 49: 20-pin, 4.40 mm body, 0.65 mm pitch D 20 11 c E1 1 E 10 k aaa CP A1 A L A2 L1 b e YA_ME Table 56: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data Dim. (1) mm Min inches Typ A Min Typ 1.200 A1 0.050 A2 0.800 b Max 0.0472 0.150 0.0020 1.050 0.0315 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 D 6.400 6.500 6.600 0.2520 0.2559 0.2598 E 6.
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STM8S103K3 STM8S103F3 STM8S103F2 Dim. (1) mm inches Min k Package information Typ 0.0° aaa (1) 11.6 Max Min 8.0° 0.0° Typ Max 8.0° 0.100 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits 20-pin SO package mechanical data Figure 50: 20-lead, plastic small outline (300 mils) package D 20 11 h x 45° C E 1 H 10 A B A1 e ddd A1 k L Z7_ME Table 57: 20-lead, plastic small outline (300 mils) mechanical data Dim.
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Package information Dim. STM8S103K3 STM8S103F3 STM8S103F2 (1) mm inches Min Typ Min Typ 10.000 10.650 0.3937 0.4193 h 0.250 0.750 0.0098 0.0295 L 0.400 1.270 0.0157 0.0500 k 0.0° 8.0° 0.0° 8.0° (1) 0.100 0.0039 Values in inches are converted from mm and rounded to 4 decimal digits UFQFPN recommended footprint Figure 51: Recommended footprint for on-board emulation 0.5mm 0.8mm [0.032"] 4mm [0.157"] 0.5mm 1.65mm [0.065"] 0.9mm [0.035"] 0.3mm [0.012"] 4mm [0.
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STM8S103K3 STM8S103F3 STM8S103F2 Package information Figure 52: Recommended footprint without on-board emulation 1. Drawing is not to scale 2.
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Thermal characteristics 12 STM8S103K3 STM8S103F3 STM8S103F2 Thermal characteristics The maximum chip junction temperature (TJ max) must never exceed the values given in Operating conditions.
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STM8S103K3 STM8S103F3 STM8S103F2 12.1 Thermal characteristics Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 12.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code. The following example shows how to calculate the temperature range needed for a given application.
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Ordering information 13 STM8S103K3 STM8S103F3 STM8S103F2 Ordering information Figure 53: STM8S103x access line ordering information scheme Example: STM8 S 103 K 3 T 6 TR Product class STM8 microcontroller Family type S = Standard Sub-family type 10x = Access line 103 sub-family Pin count K = 32 pins F = 20 pins Program memory size 3 = 8 Kbytes 2 = 4 Kbytes Package type 1 B = SDIP T = LQFP U = UFQFPN P = TSSOP M = SO Temperature range 3 = -40 °C to 125 °C 6 = -40 °C to 85 °C Package pitch Blank =
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STM8S103K3 STM8S103F3 STM8S103F2 Ordering information Address ............................................................................................. Contact ............................................................................................. Phone no. ............................................................................................. a Reference FASTROM code .............................................................................................
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Ordering information STM8S103K3 STM8S103F3 STM8S103F2 OPT0 memory readout protection (check only one option) [ ] Disable or [ ] Enable OPT1 user boot code area (UBC) 0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below.
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STM8S103K3 STM8S103F3 STM8S103F2 AFR5 (check only one option) Ordering information [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description [ ] 1: Port D0 alternate function = CLK_CCO AFR6 (check only one option) [ ] 0: Remapping option inactive. Default alternate functions used.
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Ordering information (check only one option) WWDG_HW (check only one option) IWDG_HW (check only one option) LSI_EN (check only one option) HSITRIM (check only one option) STM8S103K3 STM8S103F3 STM8S103F2 [ ] 1: Reset generated on halt if WWDG active [ ] 0: WWDG activated by software [ ] 1: WWDG activated by hardware [ ] 0: IWDG activated by software [ ] 1: IWDG activated by hardware [ ] 0: LSI clock is not available as CPU clock source [ ] 1: LSI clock is available as CPU clock source [ ] 0: 3-bit trimm
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STM8S103K3 STM8S103F3 STM8S103F2 14 STM8 development tools STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 14.
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STM8 development tools 14.2.1 STM8S103K3 STM8S103F3 STM8S103F2 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu.
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STM8S103K3 STM8S103F3 STM8S103F2 15 Revision history Revision history Table 59: Document revision history Date 02-Mar-2009 10-Apr-2009 Revision 1 2 Changes Initial revision Added Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. Updated Auto wakeup counter. Modified description of PB4 and PB5 (removed X in PP column) and added footnote concerning HS I/Os in VFQFPN32/LQFP32 pin description and STM8S103Kx UFQFPN32/LQFP32/SDIP32 pinout and pin description.
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Revision history Date STM8S103K3 STM8S103F3 STM8S103F2 Revision Changes Updated Table 19: General operating conditions. Updated name of Figure. Typical HSI accuracy at VDD = 5V vs 5 temperatures. Updated Table 43: SPI characteristics and added TBD data. Added max values to Table 46: ADC accuracy with RAIN < 10 kΩ , VDD= 5 V and Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V in the 10-bit ADC characteristics. Updated EMC characteristics.
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STM8S103K3 STM8S103F3 STM8S103F2 Date Revision Revision history Changes Updated maximum power dissipation in Table 19: General operating conditions. Updated ΘJA in Table 58: Thermal characteristics. Replaced package pitch digit by VFQFPN/UFQFPN package digit in Figure 53: STM8S103x access line ordering information scheme, and removed note 1. 09-Sep-2010 6 Removed VFQFPN32 package. Removed internal reference voltage from Analog-to-digital converter (ADC1).
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Revision history Date STM8S103K3 STM8S103F3 STM8S103F2 Revision Changes Added note for Px_IDR registers in Table 7: I/O port hardware register map. Added recommendation concerning NRST pin level, and power consumption sensitive applications, above Figure 38: Recommended reset pin protection. Removed typical HSI accuracy curve in Internal clock sources and timing characteristics.
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STM8S103K3 STM8S103F3 STM8S103F2 Please Read Carefully Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.