Datasheet

Unit
Fast mode I
2
C
(1)
Standard mode I
2
C
ParameterSymbol
Max
(2)
Min
(2)
Max
(2)
Min
(2)
-0.6-4.0STOP condition setup timet
su(STO)
μs-1.3-4.7
STOP to START condition time
(bus free)
t
w(STO:STA)
pF400-400Capacitive load for each bus lineC
b
(1)
f
MASTER
, must be at least 8 MHz to achieve max fast I
2
C speed (400kHz)
(2)
Data based on standard I
2
C protocol requirement, not tested in production
(3)
The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time
(4)
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
Figure 42: Typical application with I
2
C bus and timing diagram
t
f(SDA)
t
r(SDA)
t
su(SDA)
t
h(SDA)
t
f(SCL)
t
r(SCL)
t
w(SCLL)
t
w(SCLH)
t
h(STA)
t
su(STO)
t
su(STA)
t
w(STO:STA)
SDA
SCL
4.7kΩ
SDA
SCL
100Ω
100Ω
4.7kΩ
I
2
C bus
START
START
STOP
REPEATED
START
STM8S
V
DD
V
DD
ai17490
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
10-bit ADC characteristics10.3.10
Subject to general operating conditions for V
DD
, f
MASTER
, and T
A
unless otherwise specified.
DocID15441 Rev 986/117
STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics