Datasheet

Figure 39: SPI timing diagram - slave mode and CPHA = 0
ai14134
SCK Input
CPHA=0
MOSI
INPUT
MISO
OUT P UT
CPHA=0
MSB O UT
M SB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
Figure 40: SPI timing diagram - slave mode and CPHA = 1
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT P UT
CPHA=1
MSB O UT
M SB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
NSS input
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
DocID15441 Rev 984/117
STM8S103K3 STM8S103F3 STM8S103F2Electrical characteristics