Datasheet

Interrupt vector mapping7
Table 10: Interrupt mapping
Vector addressWakeup from
active-halt mode
Wakeup from
halt mode
DescriptionSource
block
IRQ
no.
0x00 8000YesYesResetRESET
0x00 8004--Software interruptTRAP
0x00 8008--External top level interruptTLI0
0x00 800CYes-Auto wake up from haltAWU1
0x00 8010--Clock controllerCLK2
0x00 8014Yes
(1)
Yes
(1)
Port A external interruptsEXTI03
0x00 8018YesYesPort B external interruptsEXTI14
0x00 801CYesYesPort C external interruptsEXTI25
0x00 8020YesYesPort D external interruptsEXTI36
0x00 8024YesYesPort E external interruptsEXTI47
0x00 8028--Reserved8
0x00 802C--Reserved9
0x00 8030YesYesEnd of transferSPI10
0x00 8034--TIM1 update/ overflow/ underflow/
trigger/ break
TIM1
11
0x00 8038--TIM1 capture/ compareTIM112
0x00 803C--TIM2 update/ overflowTIM213
0x00 8040--TIM2 capture/ compareTIM214
0x00 8044--Reserved15
0x00 8048--Reserved16
0x00 804C--Tx completeUART117
0x00 8050--Receive register DATA FULLUART118
0x00 8054YesYesI
2
C interruptI
2
C19
0x00 8058--Reserved20
0x00 805C--Reserved21
0x00 8060--ADC1 end of conversion/ analog
watchdog interrupt
ADC1
22
DocID15441 Rev 942/117
STM8S103K3 STM8S103F3 STM8S103F2Interrupt vector mapping