Datasheet

Reset

status

0x00Configurable clock control registerCLK_CCOR0x00 50C9

0xFFPeripheral clock gating register 2CLK_PCKENR20x00 50CA

0x00HSI clock calibration trimming

CLK_HSITRIMR0x00 50CC

0bXXXX

XXX0

SWIM clock control registerCLK_SWIMCCR0x00 50CD

ReservLK ed area (3 bytes)0x00 50CE to

0x00 50D0

0x7FWWDG control registerWWDG_CRWWDG0x00 50D1

0x7FWWDR window registerWWDG_WR0x00 50D2

Reserved area (13 bytes)0x00 50D3 to 00

50DF

0xXX

(2)

IWDG key registerIWDG_KRIWDG0x00 50E0

0x00IWDG prescaler registerIWDG_PR0x00 50E1

0xFFIWDG reload registerIWDG_RLR0x00 50E2

Reserved area (13 bytes)0x00 50E3 to

0x00 50EF

0x00AWU control/status register 1AWU_CSR1AWU0x00 50F0

0x3FAWU asynchronous prescaler buffer

AWU_APR0x00 50F1

0x00AWU timebase selection registerAWU_TBR0x00 50F2

0x1FBEEP control/status registerBEEP_CSRBEEP0x00 50F3

DocID15441 Rev 932/117

STM8S103K3 STM8S103F3 STM8S103F2Memory and register map