Datasheet
Alternate function
after remap [option
bit]
Default
alternate
function
Main
function
(after
reset)
OutputInput
TypePin name
Pin no.
PPODSpeed
High sink
(1)
Ext.
interr.
wpufloatingUFQFPN20TSSOP/SO20
Analog input 6/
UART1 data
receive
Port D6XXO3HSXXXI/OPD6/ AIN6/
UART1 _RX
203
ResetXI/ONRST14
Resonator/
crystal in
Port A1XXO1XXXI/O
PA1/ OSCIN
(2)
25
Resonator/
crystal out
Port A2XXO1XXXI/OPA2/ OSCOUT36
Digital groundSV
SS
47
1.8 V regulator capacitorSVCAP58
Digital power supplySV
DD
69
SPI master/ slave
select [AFR1]
Timer 2
channel 3
Port A3XXO3HSXXXI/OPA3/ TIM2_ CH3
[SPI_ NSS]
710
Timer 1 - break
input [AFR4]
I
2
C dataPort B5T
(3)
O1XXI/OPB5/ I
2
C_ SDA
[TIM1_ BKIN]
811
ADC external
trigger [AFR4]
I
2
C clockPort B4T
(3)
O1XXI/OPB4/ I
2
C_ SCL912
Top level interrupt
[AFR3] Timer 1 -
Timer 1 -
channel 3
Port C3XXO3HSXXXI/OPC3/ TIM1_CH3
[TLI] [TIM1_
CH1N]
1013
inverted channel 1
[AFR7]
Timer 1 - inverted
channel 2 [AFR7]
Configurable
clock
output/Timer 1
Port C4XXO3HSXXXI/OPC4/ CLK_CCO/
TIM1_
CH4/AIN2/[TIM1_
CH2N]
1114
- channel
4/Analog input
2
Timer 2 - channel 1
[AFR0]
SPI clockPort C5XXO3HSXXXI/OPC5/ SPI_SCK
[TIM2_ CH1]
1215
Timer 1 - channel 1
[AFR0]
SPI master
out/slave in
Port C6XXO3HSXXXI/OPC6/ SPI_MOSI
[TIM1_ CH1]
1316
Timer 1 - channel 2
[AFR0]
SPI master in/
slave out
Port C7XXO3HSXXXI/OPC7/ SPI_MISO
[TIM1_ CH2]
1417
SWIM data
interface
Port D1XXO4HSXXXI/OPD1/ SWIM1518
Timer 2 - channel 3
[AFR1]
Analog input 3Port D2XXO3HSXXXI/OPD2/AIN3/[TIM2_
CH3]
1619
Analog input 4/
Timer 2 -
Port D3XXO3HSXXXI/OPD3/ AIN4/ TIM2_
CH2/ ADC_ ETR
1720
channel 2/ADC
external trigger
(1)
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute
maximum ratings.
(2)
When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output
state of PA1 is not driven. It is recommended to use PA1 only in input mode if halt/active-halt is used in the application.
(3)
In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to V
DD
are not implemented).
DocID15441 Rev 926/117
STM8S103K3 STM8S103F3 STM8S103F2Pinout and pin description