Datasheet

Memory and register map STM8L15xx8, STM8L15xR6
54/134 DocID17943 Rev 6
0x00 53AC
DAC
DAC_DORH DAC data output register high 0x00
0x00 53AD DAC_DORL DAC data output register low 0x00
0x00 53A2
DAC_DCH2RDHRH
DAC channel 2 right aligned data holding
register high
0x00
0x00 53A3
DAC_DCH2RDHRL
DAC channel 2 right aligned data holding
register low
0x00
0x00 53A4
DAC_DCH1LDHRH
DAC channel 1left aligned data holding
register high
0x00
0x00 53A5
DAC_DCH1LDHRL
DAC channel 1left aligned data holding
register low
0x00
0x00 53A6
DAC_DCH2LDHRH
DAC channel 2 left aligned data holding
register high
0x00
0x00 53A7
DAC_DCH2LDHRL
DAC channel 2 left aligned data holding
register low
0x00
0x00 53A8
DAC_DCH1DHR8
DAC channel 1 8-bit mode data holding
register
0x00
0x00 53A9
DAC_DCH2DHR8
DAC channel 2 8-bit mode data holding
register
0x00
0x00 53AA to
0x00 53AB
Reserved area (2 bytes)
0x00 53AC
DAC
DAC_CH1DORH
Reset value
DAC channel 1 data output register high 0x00
0x00 53AD
DAC_CH1DORL
Reset value
DAC channel 1 data output register low 0x00
0x00 53AE
to 0x00 53AF
Reserved area (2 bytes)
0x00 53B0
DAC
DAC_CH2DORH
Reset value
DAC channel 2 data output register high 0x00
0x00 53B1
DAC_CH2DORL
Reset value
DAC channel 2 data output register low 0x00
0x00 53B2
to 0x00 53BF
Reserved area
0x00 53C0
SPI2
SPI2_CR1 SPI2 control register 1 0x00
0x00 53C1 SPI2_CR2 SPI2 control register 2 0x00
0x00 53C2 SPI2_ICR SPI2 interrupt control register 0x00
0x00 53C3 SPI2_SR SPI2 status register 0x02
0x00 53C4 SPI2_DR SPI2 data register 0x00
0x00 53C5 SPI2_CRCPR SPI2 CRC polynomial register 0x07
0x00 53C6 SPI2_RXCRCR SPI2 Rx CRC register 0x00
0x00 53C7 SPI2_TXCRCR SPI2 Tx CRC register 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status