Datasheet

DocID17943 Rev 6 133/134
STM8L15xx8, STM8L15xR6 Revision history
133
03-Apr-2013 5
Updated capacitive sensing channels and “Dynamic consumption” in
Features
Updated LCD feature in Table 2: High density and medium+ density
STM8L15xx low power device features and peripheral counts
Updated Halt mode definition in Section 3.1: Low power modes
Added Bootloader
Updated Section 3.12: System configuration controller and routing
interface
Added Section 3.13: Touch sensing
Table 5: High density and medium+ density STM8L15x pin description:
updated NRST/PA1, PI0, PI1, PI2, PE0, PE1, PE2, PF4, PF5, PF6,
PF7, footnote 1. and added Note:
Updated ‘0x00 502E to 0x00 5049’ reserved area in Table 9: General
hardware register map
Updated reference to SWIM/DEBUG manual in Section 7: Option bytes
Updated BOR factory default settings to 0x00 in Table 12: Option byte
addresses
Corrected ROP option byte value in Table 12: Option byte addresses
Added Figure 44: Maximum dynamic current consumption on VREF+
supply pin during ADC conversion
Updated STABVREFINT max value in Table 46: Reference voltage
characteristics
Updated Figure 40: SPI1 timing diagram - master mode
Added Table 57: RAIN max for fADC = 16 MHz
Updated Max DAC_OUT in Table 50: DAC characteristics
Updated Section 9.3.12: Comparator characteristics
31-Jul-2013 6
Added ‘Top view’ footnotes under the pinout figures in Section 4: Pin
description
Updated the PF4-PF7 pins for the LQFP80 in Table 5: High density and
medium+ density STM8L15x pin description
Updated all packages:
Updated Figure 53: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
outline and Table 66: UFQFPN48 7 x 7 mm, 0.5 mm pitch, package
mechanical data
Added Figure 48: LQFP80 recommended footprint
Added ‘tape and reel’ in Table 67: Ordering information scheme
Table 68. Document revision history (continued)
Date Revision Changes