Datasheet

DocID15962 Rev 13 47/131
STM8L151xx, STM8L152xx Memory and register map
56
0x00 5280
TIM3
TIM3_CR1 TIM3 control register 1 0x00
0x00 5281 TIM3_CR2 TIM3 control register 2 0x00
0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00
0x00 5283 TIM3_ETR TIM3 external trigger register 0x00
0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00
0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00
0x00 5286 TIM3_SR1 TIM3 status register 1 0x00
0x00 5287 TIM3_SR2 TIM3 status register 2 0x00
0x00 5288 TIM3_EGR TIM3 event generation register 0x00
0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00
0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00
0x00 528B TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00
0x00 528C TIM3_CNTRH TIM3 counter high 0x00
0x00 528D TIM3_CNTRL TIM3 counter low 0x00
0x00 528E TIM3_PSCR TIM3 prescaler register 0x00
0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF
0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF
0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00
0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00
0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00
0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00
0x00 5295 TIM3_BKR TIM3 break register 0x00
0x00 5296 TIM3_OISR TIM3 output idle state register 0x00
0x00 5297 to
0x00 52AF
Reserved area (25 bytes)
Table 9. General hardware register map (continued)
Address Block Register label Register name
Reset
status