Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 8-Bit 16 MHz I/O number 54

This is information on a product in full production.

August 2013 DocID15962 Rev 13 1/131

STM8L151x4, STM8L151x6,

STM8L152x4, STM8L152x6

8-bit ultralow power MCU, up to 32 KB Flash, 1 KB Data EEPROM,

RTC, LCD, timers, USART, I2C, SPI, ADC, DAC, comparators

Datasheet - production data

Features

 Operating conditions

– Operating power supply range 1.8 V to

3.6 V (down to 1.65 V at power down)

– Temp. range: - 40 °C to 85, 105 or 125 °C

 Low power features

– 5 low power modes: Wait, Low power run

(5.1 µA), Low power wait (3 µA), Active-halt

with full RTC (1.3 µA), Halt (350 nA)

– Consumption: 195 µA/MHz + 440 µA

– Ultra-low leakage per I/0: 50 nA

– Fast wakeup from Halt: 4.7 µs

 Advanced STM8 core

– Harvard architecture and 3-stage pipeline

– Max freq. 16 MHz, 16 CISC MIPS peak

– Up to 40 external interrupt sources

 Reset and supply management

– Low power, ultra-safe BOR reset with 5

selectable thresholds

– Ultra-low-power POR/PDR

– Programmable voltage detector (PVD)

 Clock management

– 1 to 16 MHz crystal oscillator

– 32 kHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– Internal 38 kHz low consumption RC

– Clock security system

 Low power RTC

– BCD calendar with alarm interrupt

– Auto-wakeup from Halt w/ periodic interrupt

 LCD: up to 4x28 segments w/ step-up

converter

 Memories

– Up to 32 KB of Flash program memory and

1 Kbyte of data EEPROM with ECC, RWW

– Flexible write and read protection modes

– Up to 2 Kbytes of RAM

 DMA

– 4 channels; supported peripherals: ADC,

DAC, SPI, I2C, USART, timers

– 1 channel for memory-to-memory

 12-bit DAC with output buffer

 12-bit ADC up to 1 Msps/25 channels

– T. sensor and internal reference voltage

 2 ultra-low-power comparators

– 1 with fixed threshold and 1 rail to rail

– Wakeup capability

 Timers

– Two 16-bit timers with 2 channels (used as

IC, OC, PWM), quadrature encoder

– One 16-bit advanced control timer with 3

channels, supporting motor control

– One 8-bit timer with 7-bit prescaler

– 2 watchdogs: 1 Window, 1 Independent

– Beeper timer with 1, 2 or 4 kHz frequencies

 Communication interfaces

– Synchronous serial interface (SPI)

– Fast I2C 400 kHz SMBus and PMBus

– USART (ISO 7816 interface and IrDA)

 Up to 41 I/Os, all mappable on interrupt vectors

 Up to 16 capacitive sensing channels

supporting touchkey, proximity, linear touch

and rotary touch sensors

 Development support

– Fast on-chip programming and non

intrusive debugging with SWIM

– Bootloader using USART

 96-bit unique ID

Table 1. Device summary

Reference Part number

STM8L151xx

(without LCD)

STM8L151C6, STM8L151C4, STM8L151K6,

STM8L151K4, STM8L151G6, STM8L151G4

STM8L152xx

(with LCD)

STM8L152C6, STM8L152C4, STM8L152K6,

STM8L152K4

UFQFPN48

LQFP32

UFQFPN28

UFQFPN32

LQFP48

CSP

WLCSP28

www.st.com

Summary of content (131 pages)

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STM8L151x4, STM8L151x6, STM8L152x4, STM8L152x6 8-bit ultralow power MCU, up to 32 KB Flash, 1 KB Data EEPROM, RTC, LCD, timers, USART, I2C, SPI, ADC, DAC, comparators Datasheet - production data Features  Operating conditions – Operating power supply range 1.8 V to 3.6 V (down to 1.65 V at power down) – Temp. range: - 40 °C to 85, 105 or 125 °C  Low power features – 5 low power modes: Wait, Low power run (5.1 µA), Low power wait (3 µA), Active-halt with full RTC (1.
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Contents STM8L151xx, STM8L152xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8L151xx, STM8L152xx 4 3.16 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.3 USART .
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Contents STM8L151xx, STM8L152xx 9.4 10 9.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.3.9 LCD controller (STM8L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.3.12 Comparator characteristics . . . . . . .
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STM8L151xx, STM8L152xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. 6/131 STM8L151xx, STM8L152xx Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8L151xx, STM8L152xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. 8/131 STM8L151xx, STM8L152xx Recommended LQFP32 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Recommended UFQFPN32 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 UFQFPN28 package outline . . .
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STM8L151xx, STM8L152xx 1 Introduction Introduction This document describes the features, pinout, mechanical data and ordering information of the medium density STM8L15x devices (STM8L151Cx/Kx/Gx, STM8L152Cx/Kx microcontrollers with a 16-Kbyte or 32-Kbyte Flash memory density). These devices are referred to as medium density devices in the STM8L15x and STM8L16x reference manual (RM0031) and in the STM8L Flash programming manual (PM0054).
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Description 2 STM8L151xx, STM8L152xx Description The medium-density STM8L15x devices are members of the STM8L ultra-low-power 8-bit family. The medium-density STM8L15x family operates from 1.8 V to 3.6 V (down to 1.65 V at power down) and is available in the -40 to +85 °C and -40 to +125 °C temperature ranges.
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STM8L151xx, STM8L152xx 2.1 Description Device overview Table 2.
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Description 2.2 STM8L151xx, STM8L152xx Ultra-low-power continuum The ultra-low-power medium-density STM8L151xx and STM8L152xx devices are fully pinto-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features.
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STM8L151xx, STM8L152xx 3 Functional overview Functional overview Figure 1.
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Functional overview 3.1 STM8L151xx, STM8L152xx Low power modes The medium density STM8L15x devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:  Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt, event or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). Wait consumption: refer to Table 21.
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STM8L151xx, STM8L152xx Functional overview Architecture and registers  Harvard architecture  3-stage pipeline  32-bit wide program memory bus - single cycle fetching most instructions  X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations  8-bit accumulator  24-bit program counter - 16 Mbyte linear memory space  16-bit stack pointer - access to a 64 Kbyte level stack  8-bit condition code register - 7
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Functional overview STM8L151xx, STM8L152xx 3.3 Reset and supply management 3.3.1 Power supply scheme The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows:  VSS1 ; VDD1 = 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for I/Os and for the internal regulator. Provided externally through VDD1 pins, the corresponding ground pin is VSS1.  VSSA ; VDDA = 1.8 to 3.6 V, down to 1.
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STM8L151xx, STM8L152xx 3.4 Functional overview Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
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Functional overview STM8L151xx, STM8L152xx Figure 2. Medium density STM8L15x clock tree diagram CSS OSC_IN OSC_OUT HSE (1) HSE OSC 1-16 MHz SYSCLK to core and HSI HSI RC 16 MHz memory SYSCLK Prescaler /1;2;4;8;16;32;64;128 LSI LSE (2) Peripheral Clock enable (15 bits) LSE (2) CLKBEEPSEL[1:0] LSI LSI RC 38 k Hz RTCSEL[3:0] OSC32_IN OSC32_OUT BEEPCLK to BEEP IWDGCLK to IWDG RTCCLK to RTC LCD peripheral clock enable (1 bit) RTC prescaler /1;2;4;8;16;32;64 LSE OSC 32 .
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STM8L151xx, STM8L152xx 3.6 Functional overview LCD (Liquid crystal display) The liquid crystal display drives up to 4 common terminals and up to 28 segment terminals to drive up to 112 pixels.  Internal step-up converter to guarantee contrast control whatever VDD.  Static 1/2, 1/3, 1/4 duty supported.  Static 1/2, 1/3 bias supported.  Phase inversion to reduce power consumption and EMI.  Up to 4 pixels which can programmed to blink.  The LCD controller can operate in Halt mode.
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Functional overview 3.10 STM8L151xx, STM8L152xx Digital-to-analog converter (DAC)  12-bit DAC with output buffer  Synchronized update capability using TIM4  DMA capability  External triggers for conversion  Input reference voltage VREF+ for better resolution Note: DAC can be served by DMA1. 3.11 Ultra-low-power comparators The medium-density STM8L15x embeds two comparators (COMP1 and COMP2) sharing the same current bias and voltage reference.
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STM8L151xx, STM8L152xx Functional overview Reliable touch sensing solutions can be quickly and easily implemented using the free STM8 Touch Sensing Library. 3.14 Timers Medium density STM8L15x devices contain one advanced control timer (TIM1), two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). All the timers can be served by DMA1. Table 3 compares the features of the advanced control, general-purpose and basic timers. Table 3.
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Functional overview 3.14.2 3.14.
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STM8L151xx, STM8L152xx Functional overview 3.17 Communication interfaces 3.17.1 SPI The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices.
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Functional overview 3.19 STM8L151xx, STM8L152xx Development support Development tools Development tools for the STM8 microcontrollers include:  The STice emulation system offering tracing and code profiling  The STVD high-level language debugger including C compiler, assembler and integrated development environment  The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.
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STM8L151xx, STM8L152xx Pin description PE7 PE6 PC7 PC6 PC5 PC4 PC3 PC2 VSS2 VDD2 PC1 PC0 Figure 3. STM8L151Cx 48-pin pinout (without LCD) 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 24 13 14 15 16 17 18 19 20 21 22 23 PD7 PD6 PD5 PD4 PF0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 Res. (1) PE0 PE1 PE2 PE3 PE4 PE5 PD0 PD1 PD2 PD3 PB0 PA0 NRST/PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS1/VSSA/VREFVDD1 VDDA VREF+ MS32628V1 1. Reserved. Must be tied to VDD.
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Pin description STM8L151xx, STM8L152xx Figure 6. STM8L151Gx WLCSP28 package pinout 4 3 2 1 A PA0 PC5 PC3 PC1 B PA2 PC6 PC2 PC0 C PA3 PA1 PC4 PD4 D PA5 PA4 PB4 PB5 E PD2 PB0 PB3 PB7 F VREF- PD3 PB2 PB6 G VREF+ PD0 PD1 PB1 ai17084 PE7 PE6 PC7 PC6 PC5 PC4 PC3 PC2 VSS2 VDD2 PC1 PC0 Figure 7.
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STM8L151xx, STM8L152xx Pin description Table 4. Legend/abbreviation for table 5 Type I= input, O = output, S = power supply Level FT Five-volt tolerant TT 3.6 V tolerant Output HS = high sink/source (20 mA) Port and control Input configuration Output float = floating, wpu = weak pull-up T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e.
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Pin description STM8L151xx, STM8L152xx Table 5.
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STM8L151xx, STM8L152xx Pin description Table 5.
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Pin description STM8L151xx, STM8L152xx Table 5.
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STM8L151xx, STM8L152xx Pin description Table 5. Medium density STM8L15x pin description (continued) PC3/USART1_TX/ LCD_SEG23(2)/ 42 28 24 A2 ADC1_IN5/COMP1_INP/ COMP2_INM TT I/O (3) X PC4/USART1_CK/ I2C1_SMB/CCO/ TT I/O (3) X 43 29 25 C2 LCD_SEG24(2)/ ADC1_IN4/COMP2_INM/ COMP1_INP X X X X Main function (after reset) PP OD High sink/source Output Ext.
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Pin description STM8L151xx, STM8L152xx Table 5. Medium density STM8L15x pin description (continued) - - - 10 - PD1/TIM1_CH3/ [TIM3_ETR](4)/ TT 9 G2 LCD_COM3(2)/ I/O (3) X ADC1_IN21/COMP2_INP/ COMP1_INP PD2/TIM1_CH1 TT 22 11 10 E4 /LCD_SEG8(2)/ I/O (3) X ADC1_IN20/COMP1_INP 23 12 32/131 - PD3/ TIM1_ETR/ TT I/O (3) X - LCD_SEG9(2)/ ADC1_IN19/COMP1_INP X X X X X X X X X X X X Main function (after reset) PP OD High sink/source Output Ext.
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STM8L151xx, STM8L152xx Pin description Table 5. Medium density STM8L15x pin description (continued) - - PD3/ TIM1_ETR/ LCD_SEG9(2)/ 11 F3 ADC1_IN19/TIM1_BKIN/ COMP1_INP/ RTC_CALIB TT I/O (3) X PD4/TIM1_CH2 TT I/O (3) X 33 21 20 C1 /LCD_SEG18(2)/ ADC1_IN10/COMP1_INP X X X X Main function (after reset) PP OD High sink/source Output Ext.
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Pin description STM8L151xx, STM8L152xx Table 5. Medium density STM8L15x pin description (continued) High sink/source PE2/TIM1_CH3N /LCD_SEG3(2) TT I/O (3) X X X HS X Timer 1 - inverted X Port E2 channel 3 / LCD segment 3 17 - - - PE3/LCD_SEG4(2) TT I/O (3) X X X HS X X Port E3 LCD segment 4 18 - - - PE4/LCD_SEG5(2) TT I/O (3) X X X HS X X Port E4 LCD segment 5 Main function (after reset) Ext.
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STM8L151xx, STM8L152xx Pin description Table 5. Medium density STM8L15x pin description (continued) 1 PA0(9)/[USART1_CK](4)/ 32 28 A4 SWIM/BEEP/IR_TIM (10) S I/O Main function (after reset) PP OD High sink/source Output Ext.
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Memory and register map STM8L151xx, STM8L152xx 5 Memory and register map 5.1 Memory mapping The memory map is shown in Figure 9. Figure 9.
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STM8L151xx, STM8L152xx Memory and register map Table 6. Flash and RAM boundary addresses Memory area Size Start address End address RAM 2 Kbytes 0x00 0000 0x00 07FF 16 Kbytes 0x00 8000 0x00 BFFF 32 Kbytes 0x00 8000 0x00 FFFF Flash program memory 5.2 Register map Table 7.
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Memory and register map STM8L151xx, STM8L152xx Table 8.
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STM8L151xx, STM8L152xx Memory and register map Table 9.
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Memory and register map STM8L151xx, STM8L152xx Table 9.
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STM8L151xx, STM8L152xx Memory and register map Table 9.
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Memory and register map STM8L151xx, STM8L152xx Table 9.
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STM8L151xx, STM8L152xx Memory and register map Table 9.
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Memory and register map STM8L151xx, STM8L152xx Table 9.
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STM8L151xx, STM8L152xx Memory and register map Table 9.
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Memory and register map STM8L151xx, STM8L152xx Table 9.
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STM8L151xx, STM8L152xx Memory and register map Table 9.
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Memory and register map STM8L151xx, STM8L152xx Table 9.
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STM8L151xx, STM8L152xx Memory and register map Table 9.
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Memory and register map STM8L151xx, STM8L152xx Table 9.
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STM8L151xx, STM8L152xx Memory and register map Table 9.
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Memory and register map STM8L151xx, STM8L152xx Table 9.
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STM8L151xx, STM8L152xx Memory and register map Table 10.
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Memory and register map STM8L151xx, STM8L152xx Table 10.
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STM8L151xx, STM8L152xx 6 Interrupt vector mapping Interrupt vector mapping Table 11. Interrupt mapping IRQ No.
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Interrupt vector mapping STM8L151xx, STM8L152xx Table 11.
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STM8L151xx, STM8L152xx 7 Option bytes Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 12 for details on option byte addresses.
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Option bytes STM8L151xx, STM8L152xx Table 13. Option byte description Option byte Option description No. OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Disable readout protection (write access via SWIM protocol) Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031). OPT1 UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01: the UBC contains only the interrupt vectors. 0x02: Page 0 and 1 reserved for the UBC and read/write protected.
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STM8L151xx, STM8L152xx Option bytes Table 13. Option byte description (continued) Option byte Option description No. OPT5 BOR_ON: 0: Brownout reset off 1: Brownout reset on BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 23 for details on the thresholds according to the value of BOR_TH bits. OPTBL OPTBL[15:0]: This option is checked by the boot ROM code after reset.
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Unique ID 8 STM8L151xx, STM8L152xx Unique ID STM8 devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.
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STM8L151xx, STM8L152xx Electrical parameters 9 Electrical parameters 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range).
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Electrical parameters 9.1.5 STM8L151xx, STM8L152xx Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 11. Pin input voltage STM8L PIN VIN MS32618V1 9.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied.
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STM8L151xx, STM8L152xx Electrical parameters Table 16. Current characteristics Symbol Ratings Max.
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Electrical parameters 9.3 STM8L151xx, STM8L152xx Operating conditions Subject to general operating conditions for VDD and TA. 9.3.1 General operating conditions Table 18. General operating conditions Symbol fSYSCLK(1) VDD VDDA Parameter System clock frequency Analog operating voltage PD(3) Power dissipation at TA= 125 °C for suffix 3 devices and at TA= 105 °C for suffix 7 devices TJ Min. Max. Unit 1.65 V VDD  3.6 V 0 16 MHz 1.65(2) 3.6 V 1.65(2) 3.6 V 1.8 3.
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STM8L151xx, STM8L152xx 9.3.2 Electrical parameters Embedded reset and power control block characteristics Table 19. Embedded reset and power control block characteristics Symbol Parameter Conditions Min VDD rise time rate BOR detector enabled 0(1) VDD fall time rate BOR detector enabled tVDD tTEMP Reset release delay Typ Max Unit (1) µs/V (1)  (1) 20 VDD rising BOR detector enabled 3 VDD rising BOR detector disabled 1 ms VPDR Power-down reset threshold Falling edge 1.
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Electrical parameters STM8L151xx, STM8L152xx 1. Data guaranteed by design, not tested in production. 2. Data based on characterization results, not tested in production. Figure 12. POR/BOR thresholds Vdd Vdd 3.6 V Operating power supply Vdd 1.
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STM8L151xx, STM8L152xx Electrical parameters Table 20. Total current consumption in Run mode Symbol Max Para meter Conditions(1) 0.39 0.47 0.49 0.52 0.55 fCPU = 1 MHz 0.48 0.56 0.58 0.61 0.65 fCPU = 4 MHz 0.75 0.84 0.86 0.91 0.99 fCPU = 8 MHz 1.10 1.20 1.25 1.31 1.40 fCPU = 16 MHz 1.85 1.93 2.12(8) 2.29(8) 2.36(8) fCPU = 125 kHz 0.05 0.06 0.09 0.11 0.12 0.18 0.19 0.20 0.22 0.23 0.55 0.62 0.64 0.71 0.77 0.99 1.20 1.21 1.22 1.24 1.90 2.22 2.23(8) 2.
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Electrical parameters STM8L151xx, STM8L152xx 5. CPU executing typical data processing 6. The run from RAM consumption can be approximated with the linear formula: IDD(run_from_RAM) = Freq * 90 µA/MHz + 380 µA 7. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (IDD HSE) must be added. Refer to Table 31. 8. Tested in production. 9.
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STM8L151xx, STM8L152xx Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 21. Total current consumption in Wait mode Max Symbol Parameter Conditions(1) HSI CPU not clocked, all peripherals OFF, Supply code executed IDD(Wait) current in from RAM Wait mode with Flash in IDDQ mode(5), VDD from 1.65 V to 3.6 V Typ 55°C 85 105 °C 125 °C Unit (3) (4) °C(2) fCPU = 125 kHz 0.33 0.39 0.41 0.43 0.45 fCPU = 1 MHz 0.35 0.41 0.44 0.
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Electrical parameters STM8L151xx, STM8L152xx Table 21. Total current consumption in Wait mode Max Conditions(1) Symbol Parameter 55°C 85 105 °C 125 °C Unit (3) (4) °C(2) fCPU = 125 kHz 0.38 0.48 0.49 0.50 0.56 fCPU = 1 MHz 0.41 0.49 0.51 0.53 0.59 fCPU = 4 MHz 0.50 0.57 0.58 0.62 0.66 fCPU = 8 MHz 0.60 0.66 0.68 0.72 0.74 fCPU = 16 MHz 0.79 0.84 0.86 0.87 0.90 fCPU = 125 kHz 0.06 0.08 0.09 0.10 0.12 fCPU = 1 MHz 0.10 0.17 0.18 0.19 0.22 fCPU = 4 MHz 0.24 0.
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STM8L151xx, STM8L152xx Electrical parameters Figure 14. Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1) 1000 950 IDD(WAIT)HSI [μA] 900 850 800 750 700 -40°C 25°C 90°C 130°C 650 600 550 500 1.6 2.1 2.6 VDD [V] 3.1 3.6 ai18214 1. Typical current consumption measured with code executed from Flash memory.
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Electrical parameters STM8L151xx, STM8L152xx In the following table, data is based on characterization results, unless otherwise specified. Table 22. Total current consumption and timing in Low power run mode at VDD = 1.65 V to 3.6 V Symbol Conditions(1) Parameter all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(2) IDD(LPR) Supply current in Low power run mode all peripherals OFF (3) external LSE clock (32.768 kHz) with TIM2 active (2) Typ Max TA = -40 °C to 25 °C 5.1 5.
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STM8L151xx, STM8L152xx Electrical parameters Figure 15. Typ. IDD(LPR) vs. VDD (LSI clock source) 18 16 –40° C 14 25° C IDD(LPR)LSI [μA] 12 90° C 10 130° C 8 6 4 2 0 1.6 2.1 2.6 VDD [V] DocID15962 Rev 13 3.1 3.
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Electrical parameters STM8L151xx, STM8L152xx In the following table, data is based on characterization results, unless otherwise specified. Table 23. Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V Symbol Conditions(1) Parameter Typ Max Unit TA = -40 °C to 25 °C all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(2) IDD(LPW) Supply current in Low power wait mode all peripherals OFF LSE external clock(3) (32.768 kHz) with TIM2 active (2) 3 3.3 TA = 55 °C 3.
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STM8L151xx, STM8L152xx Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 24. Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V Symbol Conditions (1) Parameter Typ Max TA = -40 °C to 25 °C 0.9 2.1 TA = 55 °C 1.2 3 TA = 85 °C 1.5 3.4 TA = 105 °C 2.6 6.6 TA = 125 °C 5.1 12 TA = -40 °C to 25 °C 1.4 3.1 TA = 55 °C 1.5 3.3 TA = 85 °C 1.9 4.3 TA = 105 °C 2.9 6.
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Electrical parameters STM8L151xx, STM8L152xx Table 24. Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V Symbol Conditions (1) Parameter Typ Max TA = -40 °C to 25 °C 0.5 1.2 TA = 55 °C 0.62 1.4 TA = 85 °C 0.88 2.1 TA = 105 °C 2.1 4.85 TA = 125 °C 4.8 11 TA = -40 °C to 25 °C 0.85 1.9 TA = 55 °C 0.95 2.2 TA = 85 °C 1.3 3.2 TA = 105 °C 2.3 5.3 TA = 125 °C 5.0 12 TA = -40 °C to 25 °C 1.5 2.5 TA = 55 °C 1.6 3.8 TA = 85 °C 1.8 4.
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STM8L151xx, STM8L152xx Electrical parameters Table 25. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal Symbol Condition(1) Parameter VDD = 1.8 V IDD(AH) (2) Supply current in Active-halt mode VDD = 3 V VDD = 3.6 V Typ LSE Unit 1.15 (3) LSE/32 1.05 LSE 1.30 LSE/32(3) 1.20 LSE 1.45 (3) µA 1.35 LSE/32 1. No floating I/O, unless otherwise specified. 2. Based on measurements on bench with 32.768 kHz external crystal oscillator. 3.
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Electrical parameters STM8L151xx, STM8L152xx Current consumption of on-chip peripherals Table 27. Peripheral current consumption Symbol Typ. Parameter VDD = 3.
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STM8L151xx, STM8L152xx Electrical parameters Table 28. Current consumption under external reset Symbol IDD(RST) Parameter Conditions Supply current under external reset (1) All pins are externally tied to VDD Typ VDD = 1.8 V 48 VDD = 3 V 76 VDD = 3.6 V 91 Unit µA 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. 9.3.
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Electrical parameters STM8L151xx, STM8L152xx HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
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STM8L151xx, STM8L152xx Electrical parameters LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
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Electrical parameters STM8L151xx, STM8L152xx Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 33. HSI oscillator characteristics Symbol fHSI ACCHSI Conditions(1) Parameter Frequency Min Typ - 16 VDD = 3.0 V Accuracy of HSI oscillator (factory calibrated) VDD = 3.0 V, TA = 25 °C -1 (2) VDD = 3.
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STM8L151xx, STM8L152xx Electrical parameters Low speed internal RC oscillator (LSI) In the following table, data is based on characterization results, not tested in production. Table 34. LSI oscillator characteristics Parameter (1) Symbol fLSI Conditions(1) Frequency tsu(LSI) LSI oscillator wakeup time IDD(LSI) LSI oscillator frequency drift(3) 0 °C TA  85 °C Min Typ Max Unit 26 38 56 kHz (2) - - 200 -12 - 11 µs % 1. VDD = 1.65 V to 3.
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Electrical parameters 9.3.5 STM8L151xx, STM8L152xx Memory characteristics TA = -40 to 125 °C unless otherwise specified. Table 35. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode (1) Halt mode (or Reset) 1.65 - - V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production. Flash memory Table 36.
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STM8L151xx, STM8L152xx 9.3.6 Electrical parameters I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
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Electrical parameters STM8L151xx, STM8L152xx Table 38. I/O static characteristics Symbol VIL Conditions(1) Min Input voltage on true open-drain pins (PC0 and PC1) VSS-0.3 0.3 x VDD Input voltage on five-volt tolerant (FT) pins (PA7 and PE0) VSS-0.3 0.3 x VDD Input voltage on 3.6 V tolerant (TT) pins VSS-0.3 0.3 x VDD Input voltage on any other pin VSS-0.3 0.
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STM8L151xx, STM8L152xx Electrical parameters 6. RPU pull-up equivalent resistor based on a resistive transistor(corresponding IPU current characteristics described in Figure 24). Figure 21. Typical VIL and VIH vs VDD (high sink I/Os) 3 -40°C 25°C 90°C 130°C VIL and VIH [V] 2.5 2 1.5 1 0.5 0 1.6 2.1 2.6 VDD [V] 3.1 3.6 Figure 22. Typical VIL and VIH vs VDD (true open drain I/Os) 3 -40°C 25°C 90°C 130°C VIL and VIH [V] 2.5 2 1.5 1 0.5 0 1.6 2.1 2.6 VDD [V] DocID15962 Rev 13 3.1 3.
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Electrical parameters STM8L151xx, STM8L152xx Figure 23. Typical pull-up resistance RPU vs VDD with VIN=VSS 60 -40°C 25°C 90°C 130°C Pull-Up resistance [kΩ] 55 50 45 40 35 30 1.6 1.8 2 2.2 2.4 2.6 VDD [V] 2.8 3 3.2 3.4 3.6 Figure 24. Typical pull-up current Ipu vs VDD with VIN=VSS 120 Pull-Up current [μA] 100 80 -40°C 25°C 90°C 130°C 60 40 20 0 1.65 1.8 88/131 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] DocID15962 Rev 13 3 3.15 3.3 3.45 3.
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STM8L151xx, STM8L152xx Electrical parameters Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 39. Output driving current (high sink ports) I/O Symbol Type Output low level voltage for an I/O pin High sink VOL (1) Parameter VOH (2) Output high level voltage for an I/O pin Conditions Min Max Unit IIO = +2 mA, VDD = 3.0 V 0.45 V IIO = +2 mA, VDD = 1.8 V 0.45 V IIO = +10 mA, VDD = 3.0 V 0.7 V IIO = -2 mA, VDD = 3.0 V VDD-0.
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Electrical parameters STM8L151xx, STM8L152xx Figure 25. Typ. VOL @ VDD = 3.0 V (high sink ports) Figure 26. Typ. VOL @ VDD = 1.8 V (high sink ports) 1 0.7 -40°C 25°C 90°C 130°C 0.5 0.6 -40°C 25°C 90°C 130°C 0.5 0.4 VOL [V] VOL [V] 0.75 0.3 0.25 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 0 0 IOL [mA] 1 2 3 4 5 6 7 8 IOL [mA] ai18226 Figure 27. Typ. VOL @ VDD = 3.0 V (true open drain ports) ai18227 Figure 28. Typ. VOL @ VDD = 1.8 V (true open drain ports) 0.5 0.
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STM8L151xx, STM8L152xx Electrical parameters NRST pin Subject to general operating conditions for VDD and TA unless otherwise specified. Table 42. NRST pin characteristics Symbol Parameter Conditions Min Typ Max VIL(NRST) NRST input low level voltage (1) VSS - 0.8 VIH(NRST) NRST input high level voltage (1) 1.4 - VDD IOL = 2 mA for 2.7 V  VDD  3.6 V - - IOL = 1.5 mA for VDD < 2.
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Electrical parameters STM8L151xx, STM8L152xx Figure 32. Typical NRST pull-up current Ipu vs VDD 120 -40°C 25°C 90°C 130°C Pull-Up current [μA] 100 80 60 40 20 0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] The reset network shown in Figure 33 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max. level specified in Table 42. Otherwise the reset is not taken into account internally.
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STM8L151xx, STM8L152xx 9.3.8 Electrical parameters Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under ambient temperature, fSYSCLK frequency and VDD supply voltage conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 43.
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Electrical parameters STM8L151xx, STM8L152xx Figure 34. SPI1 timing diagram - slave mode and CPHA=0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134 Figure 35.
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STM8L151xx, STM8L152xx Electrical parameters Figure 36. SPI1 timing diagram - master mode(1) High NSS input SCK output CPHA= 0 CPOL=0 SCK output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical parameters STM8L151xx, STM8L152xx I2C - Inter IC control interface Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified. The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 44.
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STM8L151xx, STM8L152xx Electrical parameters Figure 37. Typical application with I2C bus and timing diagram 1) VDD 4.7kΩ I2C VDD 4.7kΩ BUS 100Ω SDA 100Ω SCL STM8L REPEATED START START tsu(STA) tw(STO:STA) START SDA tr(SDA) tf(SDA) tsu(SDA) th(SDA) tr(SCL) tf(SCL) STOP SCL th(STA) tw(SCLH) tw(SCLL) tsu(STO) MS32620V1 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.
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Electrical parameters 9.3.9 STM8L151xx, STM8L152xx LCD controller (STM8L152xx only) In the following table, data is guaranteed by design. Not tested in production. Table 45. LCD characteristics Symbol Parameter VLCD LCD external voltage VLCD0 LCD internal reference voltage 0 2.6 VLCD1 LCD internal reference voltage 1 2.7 VLCD2 LCD internal reference voltage 2 2.8 VLCD3 LCD internal reference voltage 3 2.9 VLCD4 LCD internal reference voltage 4 3.
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STM8L151xx, STM8L152xx 9.3.10 Electrical parameters Embedded reference voltage In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 46. Reference voltage characteristics Symbol Min Typ Max. Unit Internal reference voltage consumption - 1.4 - µA ADC sampling time when reading the internal reference voltage - 5 10 µs Internal reference voltage buffer consumption (used for ADC) - 13.5 25 µA 1.202(3) 1.224 1.
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Electrical parameters 9.3.11 STM8L151xx, STM8L152xx Temperature sensor In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 47. TS characteristics Symbol Parameter Min Typ Max. Unit V90 (1) Sensor reference voltage at 90°C ±5 °C, 0.580 0.597 0.614 V ±1 ±2 °C 1.62 1.65 mV/°C 3.
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STM8L151xx, STM8L152xx Electrical parameters In the following table, data is guaranteed by design, not tested in production. Table 49. Comparator 2 characteristics Symbol VDDA Parameter Conditions Min Typ Max(1) Unit Analog supply voltage 1.65 3.6 V TA Temperature range -40 125 °C VIN Comparator 2 input voltage range 0 VDDA V tSTART td slow td fast Fast mode 15 20 Slow mode 20 25 1.65 V VDDA  2.7 V 1.8 3.5 2.7 V VDDA  3.6 V 2.5 6 1.65 V VDDA  2.7 V 0.8 2 2.
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Electrical parameters 9.3.13 STM8L151xx, STM8L152xx 12-bit DAC characteristics In the following table, data is guaranteed by design, not tested in production. Table 50. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit V VDDA Analog supply voltage 1.8 3.6 VREF+ Reference supply voltage 1.8 VDDA IVREF IVDDA Current consumption onVREF+ supply Current consumption on VDDA supply VREF+ = 3.3 V, no load, middle code (0x800) 130 220 VREF+ = 3.
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STM8L151xx, STM8L152xx Electrical parameters In the following table, data is based on characterization results, not tested in production. Table 51.
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Electrical parameters 9.3.14 STM8L151xx, STM8L152xx 12-bit ADC1 characteristics In the following table, data is guaranteed by design, not tested in production. Table 53. ADC1 characteristics Symbol Parameter VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage IVDDA Current on the VDDA input pin IVREF+ Current on the VREF+ input pin Conditions 2.4 V VDDA 3.6 V Min Max Unit 1.8 3.6 V 2.4 VDDA V 1.8 V VDDA 2.
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STM8L151xx, STM8L152xx Electrical parameters Table 53. ADC1 characteristics (continued) Symbol tS Parameter Sampling time tconv 12-bit conversion time tWKUP Wakeup time from OFF state tIDLE(6) tVREFINT Time before a new conversion Conditions Min VAIN on PF0 fast channel VDDA < 2.4 V 0.43(4)(5) µs VAIN on PF0 fast channel 2.4 V VDDA 3.6 V 0.22(4)(5) µs VAIN on slow channels VDDA < 2.4 V 0.86(4)(5) µs VAIN on slow channels 2.4 V VDDA 3.6 V 0.
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Electrical parameters STM8L151xx, STM8L152xx In the following three tables, data is guaranteed by characterization result, not tested in production. Table 54. ADC1 accuracy with VDDA = 3.3 V to 2.5 V Symbol Parameter Conditions Typ Max 1 1.6 Differential non linearity fADC = 8 MHz 1 1.6 fADC = 4 MHz 1 1.5 fADC = 16 MHz 1.2 2 fADC = 8 MHz 1.2 1.8 fADC = 4 MHz 1.2 1.7 fADC = 16 MHz 2.2 3.0 fADC = 8 MHz 1.8 2.5 fADC = 4 MHz 1.8 2.3 fADC = 16 MHz 1.5 2 fADC = 8 MHz 1 1.
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STM8L151xx, STM8L152xx Electrical parameters Figure 38. ADC1 accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET 7 (1) 6 5 4 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one.
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Electrical parameters STM8L151xx, STM8L152xx Figure 40. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700μA 300μA MS32625V1 Table 57. RAIN max for fADC = 16 MHz(1) RAIN max (kohm) Ts (cycles) Ts (µs) Slow channels Fast channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 0.7 Not allowed 9 0.5625 0.8 Not allowed 2.0 1.
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STM8L151xx, STM8L152xx Electrical parameters Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA) STM8L V REF+ External reference 1 μF // 10 nF Supply V DDA 1 μF // 10 nF V SSA/V REF- ai17031b Figure 42.
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Electrical parameters 9.3.15 STM8L151xx, STM8L152xx EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
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STM8L151xx, STM8L152xx Electrical parameters Table 59. EMI data (1) Symbol Parameter SEMI VDD 3.6 V, TA +25 °C, LQFP32 conforming to IEC61967-2 Peak level Monitored frequency band Conditions Max vs. Unit 16 MHz 0.1 MHz to 30 MHz -3 30 MHz to 130 MHz 9 130 MHz to 1 GHz 4 SAE EMI Level 2 dBV - 1. Not tested in production.
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Electrical parameters 9.4 STM8L151xx, STM8L152xx Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 18: General operating conditions on page 64.
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STM8L151xx, STM8L152xx Package characteristics 10 Package characteristics 10.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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Package characteristics STM8L151xx, STM8L152xx 10.2 Package mechanical data 10.2.1 48-pin low profile quad flat 7x7mm package (LQFP48) Figure 43. LQFP48 package outline D ccc $ D1 " " D3 25 36 24 37 L1 b E3 E1 E 48 Pin 1 identification 13 1 L A1 K D 12 5B_ME 1. Drawing is not to scale. Table 63. LQFP48 package mechanical data Dim. inches(1) mm Min Typ A Max Min 1.6 A1 0.05 A2 1.35 b 0.17 Max 0.063 0.15 0.002 0.0059 1.4 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.
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STM8L151xx, STM8L152xx Package characteristics Figure 44. Recommended LQFP48 footprint 0.50 1.20 13 0.30 24 12 25 7.30 0.20 9.70 5.80 7.30 1 36 48 37 1.20 5.80 9.70 5B_FP_V2 1. Dimensions are in millimeters.
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Package characteristics 10.2.2 STM8L151xx, STM8L152xx 48-pin ultra thin fine pitch quad flat no-lead 7 x 7 mm, 0.5 mm pitch package (UFQFPN48) Figure 45. UFQFPN48 package outline Pin 1 indentifier laser marking area D A E E T ddd A1 Seating plane b e Detail Y D Exposed pad area Y D2 1 L 48 C 0.500x45° pin1 corner E2 R 0.125 typ. Detail Z 1 Z 48 A0B9_ME_V3 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
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STM8L151xx, STM8L152xx Package characteristics Table 64. UFQFPN48 package mechanical data Symbol A millimeters Inches Min Typ Max Min Typ Max 0.500 0.550 0.600 0.0217 0.0197 0.0236 A1 0.000 0.020 0.050 0.0008 0.0000 0.0020 D 6.900 7.000 7.100 0.2756 0.2717 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E 6.900 7.000 7.100 0.2756 0.2717 0.2795 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0157 0.0118 0.0197 0.0079 0.0118 T b 0.
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Package characteristics 10.2.3 STM8L151xx, STM8L152xx 32-pin low profile quad flat package (LQFP32) Figure 47. LQFP32 package outline ccc C D D1 D3 24 A A2 17 16 25 L1 b E3 32 Pin 1 identification E1 E 9 L A1 1 K c 8 5V_ME 1. Drawing is not to scale. Table 65. LQFP32 package mechanical data inches(1) mm Dim. Min Typ A Max Min 1.6 A1 0.05 A2 1.35 b 0.3 c 0.09 D 8.8 D1 6.8 D3 Max 0.063 0.15 0.0020 1.4 1.45 0.0531 0.0551 0.0571 0.37 0.45 0.0118 0.0146 0.0177 0.
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STM8L151xx, STM8L152xx Package characteristics Figure 48. Recommended LQFP32 footprint 0.80 1.20 0.50 0.30 7.30 6.10 9.70 7.30 1.20 6.10 9.70 5V_FP_V2 1. Dimensions are in millimeters.
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Package characteristics 10.2.4 STM8L151xx, STM8L152xx 32-lead ultra thin fine pitch quad flat no-lead 5x5 mm package (UFQFPN32) Figure 49. UFQFPN32 package outline Seating plane C ddd C A A1 A3 D e 16 9 17 8 E2 E b 24 1 L 32 Pin # 1 ID R = 0.30 D2 Bottom view L A0B8_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package.
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STM8L151xx, STM8L152xx Package characteristics Table 66. UFQFPN32 package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A 0.5 0.55 0.6 0.0197 0.0217 0.0236 A1 0.00 0.02 0.05 0 0.0008 0.0020 A3 0.152 0.006 b 0.18 0.23 0.28 0.0071 0.0091 0.0110 D 4.90 5.00 5.10 0.1929 0.1969 0.2008 D2 3.50 0.1378 E 4.90 5.00 5.10 0.1929 0.1969 0.2008 E2 3.40 3.50 3.60 0.1339 0.1378 0.1417 e L 0.500 0.30 0.0197 0.40 ddd 0.50 0.0118 0.0157 0.08 0.
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Package characteristics 10.2.5 STM8L151xx, STM8L152xx 28-lead ultra thin fine pitch quad flat no-lead 4x4 mm package (UFQFPN28) Figure 51. UFQFPN28 package outline D B D1 A Seating Plane Co 130x45° Pin 1 corner E1 E L1 1 L Pin 1 ID 28 Detail Z Detail Z Ro.125 Typ. e T A A1 Seating Plane b A0B0_ME_V4 1. Drawing is not to scale. Table 67. UFQFPN28 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 -0.
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STM8L151xx, STM8L152xx Package characteristics Figure 52. Recommended UFQFPN28 footprint (dimensions in mm) 3.30 0.50 3.20 4.30 3.30 3.20 0.30 0.55 0.50 0.50 A0B0_FP_V2 1. Dimensions are in millimeters.
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Package characteristics 10.2.6 STM8L151xx, STM8L152xx 28-pin wafer level chip size package (WLCSP28) Figure 53. WLCSP28 package outline bbb Z e1 e e Detail A e2 Notch G A2 A F Die ID Bump side Side view A2 A Bump Front view A1 eee Z D X Y Z A1 ball location b(28x) Seating plane E Detail A rotated by 90 °C aaa (4X) Wafer back side ME_A0AM 1. Drawing is not to scale.
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STM8L151xx, STM8L152xx Package characteristics Table 68. WLCSP28 package mechanical data Dim. inches(1) mm Min Typ Max Min Typ Max A 0.540 0.570 0.600 0.0213 0.0224 0.0236 A1 0.165 0.190 0.215 0.0065 0.0075 0.0085 A2 0.350 0.380 0.410 0.0138 0.0150 0.0161 b 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 1.668 1.703 1.738 0.0657 0.0670 0.0684 E 2.806 2.841 2.876 0.1105 0.1119 0.1132 e 0.400 0.0157 e1 1.200 0.0472 e2 2.400 0.0945 F 0.251 0.0099 G 0.
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Device ordering information 11 STM8L151xx, STM8L152xx Device ordering information Figure 54.
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STM8L151xx, STM8L152xx 12 Revision history Revision history Table 69. Document revision history Date Revision 06-Aug-2009 1 Initial release 2 Updated peripheral naming throughout document.
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Revision history STM8L151xx, STM8L152xx Table 69.
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STM8L151xx, STM8L152xx Table 69. Revision history Document revision history Date 11-Mar-2011 06-Sep-2011 Revision Changes 6 cont’d Modified OPT1 and OPT4 description in Table 12: Option byte description on page 50. Updated Section 9: Electrical parameters on page 53 “standard I/Os” replaced with “high sink I//Os”. Updated RHN and RHN descriptions in Table 45: LCD characteristics on page 103. Added Tape & Reel option to Figure 52: Medium density STM8L15x ordering information scheme on page 123.
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Revision history STM8L151xx, STM8L152xx Table 69. Document revision history Date Changes 8 Features: replaced “’Dynamic consumption’ with ‘Consumption’. Table 5: Medium density STM8L15x pin description: updated OD column of NRST/PA1 pin. Table 11: Interrupt mapping: removed tamper 1, tamper 2 and tamper 3. Figure 45: UFQFPN48 package outline: replaced. Table 64: UFQFPN48 package mechanical data: updated title.
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STM8L151xx, STM8L152xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.