Datasheet

STM8L151x2, STM8L151x3 Electrical parameters
Doc ID 018780 Rev 4 79/112
Figure 31. Typical NRST pull-up current I
pu
vs V
DD
The reset network shown in Figure 32 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V
IL(NRST)
max. level specified
in Ta bl e 3 8 . Otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If the NRST signal is used to reset the
external circuitry, attention must be paid to the charge/discharge time of the external
capacitor to fulfill the external devices reset timing conditions. The minimum recommended
capacity is 10 nF.
Figure 32. Recommended NRST pin configuration
0
20
40
60
80
100
120
1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6
V
DD
[V]
Pull-U
p current [μA]
-40°C
25°C
90°C
130°C
EXTERNAL
RESET
CIRCUIT
STM8
Filter
R
PU
V
DD
INTERNAL RESET
NRST
0.1 µF
(Optional)