Datasheet

STM8L151x2, STM8L151x3 Electrical parameters
Doc ID 018780 Rev 4 65/112
7.3.4 Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for V
DD
and T
A
.
LSE external clock (LSEBYP=1 in CLK_ECKCR)
Subject to general operating conditions for V
DD
and T
A
.
Table 24. Current consumption under external reset
Symbol Parameter Conditions Typ Unit
I
DD(RST)
Supply current under
external reset
(1)
All pins are externally
tied to V
DD
V
DD
= 1.8 V 48
µAV
DD
= 3 V 76
V
DD
= 3.6 V 91
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
Table 25. HSE external clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
HSE_ext
External clock source
frequency
(1)
1. Data guaranteed by Design, not tested in production.
116MHz
V
HSEH
OSC_IN input pin high level
voltage
0.7 x V
DD
V
DD
V
V
HSEL
OSC_IN input pin low level
voltage
V
SS
0.3 x V
DD
C
in(HSE)
OSC_IN input
capacitance
(1)
2.6 pF
I
LEAK_HSE
OSC_IN input leakage
current
V
SS
< V
IN
< V
DD
±1 µA
Table 26. LSE external clock characteristics
Symbol Parameter Min Typ Max Unit
f
LSE_ext
External clock source frequency
(1)
32.768 kHz
V
LSEH
(2)
OSC32_IN input pin high level voltage 0.7 x V
DD
V
DD
V
V
LSEL
(2)
OSC32_IN input pin low level voltage V
SS
0.3 x V
DD
C
in(LSE)
OSC32_IN input capacitance
(1)
0.6 pF
I
LEAK_LSE
OSC32_IN input leakage current ±1 µA
1. Data guaranteed by Design, not tested in production.
2. Data based on characterization results, not tested in production.