Datasheet

STM8L151x2, STM8L151x3 Memory and register map
Doc ID 018780 Rev 4 37/112
0x00 50C0
CLK
CLK_CKDIVR CLK clock master divider register 0x03
0x00 50C1 CLK_CRTCR CLK clock RTC register 0x00
(1)
0x00 50C2 CLK_ICKCR CLK internal clock control register 0x11
0x00 50C3 CLK_PCKENR1 CLK peripheral clock gating register 1 0x00
0x00 50C4 CLK_PCKENR2 CLK peripheral clock gating register 2 0x00
0x00 50C5 CLK_CCOR CLK configurable clock control register 0x00
0x00 50C6 CLK_ECKCR CLK external clock control register 0x00
0x00 50C7 CLK_SCSR CLK system clock status register 0x01
0x00 50C8 CLK_SWR CLK system clock switch register 0x01
0x00 50C9 CLK_SWCR CLK clock switch control register 0xX0
0x00 50CA CLK_CSSR CLK clock security system register 0x00
0x00 50CB CLK_CBEEPR CLK clock BEEP register 0x00
0x00 50CC CLK_HSICALR CLK HSI calibration register 0xXX
0x00 50CD CLK_HSITRIMR CLK HSI clock calibration trimming register 0x00
0x00 50CE CLK_HSIUNLCKR CLK HSI unlock register 0x00
0x00 50CF CLK_REGCSR CLK main regulator control status register 0bxx11 100X
0x00 50D0 CLK_PCKENR3 CLK peripheral clock gating register 3 0x00
0x00 50D1
to
0x00 50D2
Reserved area (2 bytes)
0x00 50D3
WWDG
WWDG_CR WWDG control register 0x7F
0x00 50D4 WWDG_WR WWDR window register 0x7F
0x00 50D5
to
00 50DF
Reserved area (11 bytes)
0x00 50E0
IWDG
IWDG_KR IWDG key register 0x01
0x00 50E1 IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3
to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
BEEP
BEEP_CSR1 BEEP control/status register 1 0x00
0x00 50F1
0x00 50F2
Reserved area (2 bytes)
0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F
0x00 50F4
to
0x00 513F
Reserved area (76 bytes)
Table 8. General hardware register map (continued)
Address Block Register label Register name Reset status