Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 20 8-Bit 16 MHz I/O number 18

July 2012 Doc ID 018780 Rev 4 1/112

STM8L151C2/K2/G2/F2

STM8L151C3/K3/G3/F3

8-bit ultralow power MCU, up to 8 KB Flash, up to 256 B data EEPROM,

RTC, timers, USART, I2C, SPI, ADC, comparators

Datasheet − production data

Features

■ Operating conditions

– Operating power supply: 1.65 to 3.6 V

(without BOR), 1.8 to 3.6 V (with BOR)

– Temperature range: -40 to 85 or 125 °C

■ Low power features

– 5 low power modes: Wait, Low power run,

Low power wait, Active-halt with RTC, Halt

– Ultralow leakage per I/0: 50 nA

– Fast wakeup from Halt: 5 µs

■ Advanced STM8 core

– Harvard architecture and 3-stage pipeline

– Max freq: 16 MHz, 16 CISC MIPS peak

– Up to 40 external interrupt sources

■ Reset and supply management

– Low power, ultrasafe BOR reset with 5

selectable thresholds

– Ultralow power POR/PDR

– Programmable voltage detector (PVD)

■ Clock management

– 32 kHz and 1-16 MHz crystal oscillators

– Internal 16 MHz factory-trimmed RC

– Internal 38 kHz low consumption RC

– Clock security system

■ Low power RTC

– BCD calendar with alarm interrupt

– Digital calibration with +/- 0.5 ppm accuracy

– LSE security system

– Auto-wakeup from Halt w/ periodic interrupt

■ Memories

– Up to 8 Kbytes of Flash program memory

plus 256 bytes of data EEPROM with ECC

– Flexible write/read protection modes

– 1 Kbyte of RAM

■ DMA

– 4 channels supporting ADC, SPI, I

USART, timers

– 1 channel for memory-to-memory

■ 12-bit ADC up to 1 Msps/28 channels

– Temp. sensor and internal ref. voltage

■ 2 ultralow power comparators

– 1 with fixed threshold and 1 rail to rail

– Wakeup capability

■ Timers

– Two 16-bit timers with 2 channels (IC, OC,

PWM), quadrature encoder (TIM2, TIM3)

– One 8-bit timer with 7-bit prescaler (TIM4)

– 1 Window and 1 independent watchdog

– Beeper timer with 1, 2 or 4 kHz frequencies

■ Communication interfaces

– One synchronous serial interface (SPI)

–Fast I

C 400 kHz

– One USART

■ Up to 41 I/Os, all mappable on interrupt vectors

■ Up to 20 capacitive sensing channels

supporting touchkey, proximity touch, linear

touch, and rotary touch sensors

■ Development support

– Fast on-chip programming and non-

intrusive debugging with SWIM

– Bootloader using USART

■ 96-bit unique ID

UFQFPN28

UFQFPN32

TSSOP20

UFQFPN20

LQFP48

www.st.comThis is information on a product in full production.

Summary of content (112 pages)

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STM8L151C2/K2/G2/F2 STM8L151C3/K3/G3/F3 8-bit ultralow power MCU, up to 8 KB Flash, up to 256 B data EEPROM, RTC, timers, USART, I2C, SPI, ADC, comparators Datasheet − production data Features ■ ■ ■ ■ ■ ■ ■ Operating conditions – Operating power supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.
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Contents STM8L151x2, STM8L151x3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8L151x2, STM8L151x3 4 3.15.2 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin description . . .
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Contents STM8L151x2, STM8L151x3 7.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.1 ECOPACK . . . . . . . . . . . . .
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STM8L151x2, STM8L151x3 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. 6/112 STM8L151x2, STM8L151x3 ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8L151x2, STM8L151x3 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 48. Figure 49. Figure 50. 8/112 STM8L151x2, STM8L151x3 UFQFPN20 recommended footprint (dimensions in mm). . . . . . . . . . . . . . . . . . . . . . . . . 107 TSSOP20 - 20-pin thin shrink small outline package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Low density STM8L15xxx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . .
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STM8L151x2, STM8L151x3 1 Introduction Introduction This document describes the features, pinout, mechanical data and ordering information for the Low density STM8L15xxx devices: STM8L151x2 and STM8L151x3 microcontrollers with a Flash memory density of up to 8 Kbytes. For further details on the STMicroelectronics Ultralow power family please refer to Section 2.2: Ultra-low-power continuum on page 13. For detailed information on device operation and registers, refer to the reference manual (RM0031).
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Introduction STM8L151x2, STM8L151x3 STM8L Ultralow power microcontrollers can operate either from 1.8 to 3.6 V (down to 1.65 V at power-down) or from 1.65 to 3.6 V. They are available in the -40 to +85 °C and -40 to +125 °C temperature ranges.
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STM8L151x2, STM8L151x3 2 Description Description The Low density STM8L15xxx Ultralow power devices feature an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.
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Description STM8L151x2, STM8L151x3 2.1 Device overview Table 1.
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STM8L151x2, STM8L151x3 2.2 Description Ultra-low-power continuum The ultra-low-power Low density STM8L15xxx devices are fully pin-to-pin, software and feature compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes STM8L101xx and STM32L15xxx. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture, and features. They are all based on STMicroelectronics 0.
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Functional overview STM8L151x2, STM8L151x3 3 Functional overview Figure 1. Low density STM8L151xx device block diagram OSC_IN, OSC_OUT 16 MHz internal RC OSC32_IN, OSC32_OUT @VDD 1-16 MHz oscillator 32 kHz oscillator VDD18 Clock controller and CSS VOLT. REG.
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STM8L151x2, STM8L151x3 3.1 Functional overview Low power modes The Low density STM8L15x devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Wait mode: The CPU clock is stopped, but selected peripherals keep running. An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode (WFE or WFI mode). Wait consumption: refer to Table 17.
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Functional overview STM8L151x2, STM8L151x3 Architecture and registers ● Harvard architecture ● 3-stage pipeline ● 32-bit wide program memory bus - single cycle fetching most instructions ● X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations ● 8-bit accumulator ● 24-bit program counter - 16 Mbyte linear memory space ● 16-bit stack pointer - access to a 64 Kbyte level stack ● 8-bit condition code register - 7
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STM8L151x2, STM8L151x3 Functional overview 3.3 Reset and supply management 3.3.1 Power supply scheme The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power supply pins must be connected as follows: ● VSS1 ; VDD1 = 1.8 to 3.6 V, down to 1.65 V at power down: external power supply for I/Os and for the internal regulator. Provided externally through VDD1 pins, the corresponding ground pin is VSS1. ● VSSA ; VDDA = 1.8 to 3.6 V, down to 1.
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Functional overview 3.4 STM8L151x2, STM8L151x3 Clock management The clock controller distributes the system clock (SYSCLK) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
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STM8L151x2, STM8L151x3 Figure 2. Functional overview Low density STM8L15x clock tree diagram SWIM[3:0] OSC_OUT OSC_IN HSE OSC 1-16 MHz HSE HSI HSI RC 1-16 MHz LSI SYSCLK prescaler /1;2;4;8;16;32;64 SYSCLK to core and memory PCLK to peripherals Peripheral Clock enable (13 bits) LSE LSE BEEPCLK CLKBEEPSEL[1:0] LSI LSI RC 38 kHz IWDGCLK to BEEP to IWDG RTCSEL[3:0] OSC32_OUT OSC32_IN CCO 3.5 RTC prescaler /1;2;4;8;16;32;64 LSE OSC 32.
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Functional overview 3.6 STM8L151x2, STM8L151x3 Memories The Low density STM8L15x devices have the following main features: ● Up to 1 Kbyte of RAM ● The non-volatile memory is divided into three arrays: – Up to 8 Kbytes of low-density embedded Flash program memory – 256 bytes of data EEPROM – Option bytes. The EEPROM embeds the error correction code (ECC) feature. The option byte protects part of the Flash program memory from write and readout piracy. 3.
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STM8L151x2, STM8L151x3 3.10 Functional overview System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped. The highly flexible routing interface controls the routing of internal analog signals to ADC1, COMP1, COMP2, and the internal reference voltage VREFINT.
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Functional overview 3.12.1 3.12.
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STM8L151x2, STM8L151x3 Functional overview 3.15 Communication interfaces 3.15.1 SPI The serial peripheral interface (SPI1) provides half/ full duplex synchronous serial communication with external devices.
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Functional overview 3.17 STM8L151x2, STM8L151x3 Development support Development tools Development tools for the STM8 microcontrollers include: ● The STice emulation system offering tracing and code profiling ● The STVD high-level language debugger including C compiler, assembler and integrated development environment ● The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.
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STM8L151x2, STM8L151x3 Pin description STM8L151Cx LQFP48 package pinout PE7 PE6 PC7 PC6 PC5 PC4 PC3 PC2 V SSIO V DDIO PC1 PC0 Figure 3. 48 47 46 45 44 43 42 41 40 39 38 37 PA0 NRST/PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS1 /VSSA/VREFVDD VDDA VREF+ 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 12 26 25 PD7 PD6 PD5 PD4 PF0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 MS18276V1 STM8L151Kx UFQFPN32 package pinout PA0 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Figure 4.
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Pin description STM8L151Fx UFQFPN20 package pinout PA0 PC6 PC5 PC4 PC1 Figure 6. STM8L151x2, STM8L151x3 20 19 18 17 NRST / PA1 PA2 16 PC0 PB7 1 15 2 14 PA3 3 13 VSS/VSSA/VREFVDD/VDDA/VREF+ 4 12 PB6 PB5 11 PB4 5 8 9 10 PB2 PB3 7 PD0 PB0 PB1 6 MS18279V1 Figure 7.
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STM8L151x2, STM8L151x3 Table 3. Pin description Legend/abbreviation for table 4 Type I= input, O = output, S = power supply Output HS = high sink/source (20 mA) FT Five-volt tolerant Level Port and control Input configuration Output T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state).
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Pin description Low density STM8L15xxx pin description (continued) Output Ext.
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STM8L151x2, STM8L151x3 Low density STM8L15xxx pin description (continued) Output floating wpu Ext.
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Pin description Low density STM8L15xxx pin description (continued) 1 32 28 20 PA0(8)/[USART_CK](2) / 3 I/O SWIM/BEEP/IR_TIM X X X HS (9) (9) X Main function (after reset) PP OD High sink/source Output Ext. interrupt floating I/O level Pin name Type Input TSSOP20 UFQFPN20 UFQFPN28 UFQFPN32 LQFP48 Pin number wpu Table 4.
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STM8L151x2, STM8L151x3 Memory and register map 5 Memory and register map 5.1 Memory mapping The memory map is shown in Figure 8. Figure 8.
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Memory and register map STM8L151x2, STM8L151x3 MSB have a fixed value: 0x6. 3. The TS_Factory_CONV_V90 byte represents the LSB of the V90 12-bit ADC1 conversion result. The MSB have a fixed value: 0x3. 4. Refer to Table 8 for an overview of hardware register mapping, to Table 7 for details on I/O port hardware registers, and to Table 9 for information on CPU/SWIM/debug module controller registers. Table 5.
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STM8L151x2, STM8L151x3 Table 7.
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Memory and register map Table 8.
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STM8L151x2, STM8L151x3 Table 8.
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Memory and register map Table 8.
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STM8L151x2, STM8L151x3 Table 8.
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Memory and register map Table 8.
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STM8L151x2, STM8L151x3 Table 8.
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Memory and register map Table 8.
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STM8L151x2, STM8L151x3 Table 8.
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Memory and register map Table 8.
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STM8L151x2, STM8L151x3 Table 8.
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Memory and register map Table 8.
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STM8L151x2, STM8L151x3 Table 9.
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Memory and register map Table 9.
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STM8L151x2, STM8L151x3 Interrupt vector mapping 6 Interrupt vector mapping Table 10. Interrupt mapping IRQ No.
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Interrupt vector mapping Table 10.
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STM8L151x2, STM8L151x3 Electrical parameters 7 Electrical parameters 7.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 7.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range).
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Electrical parameters 7.1.5 STM8L151x2, STM8L151x3 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 10. Pin input voltage STM8L PIN VIN 7.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied.
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STM8L151x2, STM8L151x3 Table 12. Electrical parameters Current characteristics Symbol Ratings Max. IVDD Total current into VDD power line (source) 80 IVSS Total current out of VSS ground line (sink) 80 Output current sunk by IR_TIM pin (with high sink LED driver capability) 80 Output current sunk by any other I/O and control pin 25 IIO Output current sourced by any I/Os and control pin IINJ(PIN) ΣIINJ(PIN) 1.
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Electrical parameters 7.3 STM8L151x2, STM8L151x3 Operating conditions Subject to general operating conditions for VDD and TA. 7.3.1 General operating conditions Table 14. General operating conditions Symbol fSYSCLK(1) Parameter System clock frequency VDD Standard operating voltage VDDA Analog operating voltage Conditions Min. Max. Unit 1.65 V ≤ VDD < 3.6 V 0 16 MHz 1.65(2) 3.6 V 1.65(2) 3.6 V 1.8 3.
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STM8L151x2, STM8L151x3 Electrical parameters 7.3.2 Embedded reset and power control block characteristics Table 15.
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Electrical parameters STM8L151x2, STM8L151x3 Figure 11. POR/BOR thresholds Vdd Vdd 3.6 V Operating power supply Vdd BOR threshold 1.8 V BOR Threshold_0 VBOR0 VPDR Reset Safe Reset Safe Reset release without BOR = Batte ry li fe exte nsi on PDR Threshold Internal NRST with without BOR BOR with BOR BOR activated by user for power down detection BOR always active at power up 7.3.
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STM8L151x2, STM8L151x3 Table 16. Symbol Electrical parameters Total current consumption in Run mode Max Para meter Conditions(1) Supply current IDD(RUN) in Run mode 85 °C 105°C(2) 125 °C(2) 0.39 0.47 0.49 0.52 0.55 fCPU = 1 MHz 0.48 0.56 0.58 0.61 0.65 fCPU = 4 MHz 0.75 0.84 0.86 0.91 0.99 fCPU = 8 MHz 1.10 1.20 1.25 1.31 1.40 fCPU = 16 MHz 1.85 1.93 2.12(6) 2.29(6) 2.36(6) fCPU = 125 kHz 0.05 0.06 0.09 0.11 0.12 0.18 0.19 0.20 0.22 0.23 0.55 0.62 0.64 0.
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Electrical parameters STM8L151x2, STM8L151x3 4. The run from RAM consumption can be approximated with the linear formula: IDD(run_from_RAM) = Freq * 90 µA/MHz + 380 µA 5. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (IDD HSE) must be added. Refer to Table 27. 6. Tested in production. 7. The run from Flash consumption can be approximated with the linear formula: IDD(run_from_Flash) = Freq * 195 µA/MHz + 440 µA 8.
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STM8L151x2, STM8L151x3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 17. Total current consumption in Wait mode Max Conditions(1) Symbol Parameter Typ 55°C 85 °C HSI CPU not clocked, all peripherals OFF, Supply code executed IDD(Wait) current in from RAM Wait mode with Flash in IDDQ mode(3), VDD from 1.65 V to 3.6 V (2) fCPU = 125 kHz 0.33 0.39 0.41 0.43 0.45 fCPU = 1 MHz 0.35 0.41 0.44 0.45 0.
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Electrical parameters STM8L151x2, STM8L151x3 2. For temperature range 3. 3. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register. 4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption (IDD HSE) must be added. Refer to Table 27. 5. Tested in production. 6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption (IDD HSE) must be added. Refer to Table 28.
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STM8L151x2, STM8L151x3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 18. Total current consumption and timing in Low power run mode at VDD = 1.65 V to 3.6 V Symbol Conditions(1)(2) Parameter all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(3) IDD(LPR) Supply current in Low power run mode all peripherals OFF (4) external LSE clock (32.768 kHz) with TIM2 active (3) Typ Max TA = -40 °C to 25 °C 5.1 5.
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Electrical parameters STM8L151x2, STM8L151x3 Figure 14. Typ. IDD(LPR) vs. VDD (LSI clock source) 18 16 –40° C 14 25° C IDD(LPR)LSI [μA] 12 90° C 10 130° C 8 6 4 2 0 1.6 2.1 2.6 VDD [V] 60/112 Doc ID 018780 Rev 4 3.1 3.
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STM8L151x2, STM8L151x3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 19. Symbol Total current consumption in Low power wait mode at VDD = 1.65 V to 3.6 V Conditions(1)(2) Parameter Typ Max Unit TA = -40 °C to 25 °C all peripherals OFF LSI RC osc. (at 38 kHz) with TIM2 active(3) IDD(LPW) Supply current in Low power wait mode all peripherals OFF LSE external clock(4) (32.768 kHz) with TIM2 active (3) 3 3.
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Electrical parameters STM8L151x2, STM8L151x3 In the following table, data is based on characterization results, unless otherwise specified. Table 20. Total current consumption and timing in Active-halt mode at VDD = 1.65 V to 3.6 V Symbol Conditions (1)(2) Parameter LSI RC (at 38 kHz) Supply current in Active-halt mode IDD(AH) LSE external clock (32.768 kHz) (3) IDD(WUFAH) Typ Max TA = -40 °C to 25 °C 0.9 2.1 TA = 55 °C 1.2 3 TA = 85 °C 1.5 3.4 TA = 105 °C 2.6 6.6 TA = 125 °C 5.
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STM8L151x2, STM8L151x3 Electrical parameters In the following table, data is based on characterization results, unless otherwise specified. Table 22. Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V Symbol IDD(Halt) Condition(1)(2) Parameter Supply current in Halt mode (Ultra-low-power ULP bit =1 in the PWR_CSR2 register) Typ Max TA = -40 °C to 25 °C 350 1400(3) TA = 55 °C 580 2000 TA = 85 °C 1160 2800(3) TA = 105 °C 2560 6700(3) TA = 125 °C 4.
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Electrical parameters STM8L151x2, STM8L151x3 Current consumption of on-chip peripherals Table 23. Peripheral current consumption Symbol Typ. Parameter VDD = 3.
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STM8L151x2, STM8L151x3 Table 24. Current consumption under external reset Symbol IDD(RST) Electrical parameters Parameter Conditions Supply current under external reset (1) All pins are externally tied to VDD Typ VDD = 1.8 V 48 VDD = 3 V 76 VDD = 3.6 V 91 Unit µA 1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset. 7.3.
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Electrical parameters STM8L151x2, STM8L151x3 HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
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STM8L151x2, STM8L151x3 Electrical parameters LSE crystal/ceramic resonator oscillator The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
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Electrical parameters STM8L151x2, STM8L151x3 Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 29. Symbol fHSI ACCHSI HSI oscillator characteristics Conditions(1)(2) Parameter Frequency Accuracy of HSI oscillator (factory calibrated) Min VDD = 3.0 V Typ Max 16 (3) VDD = 3.0 V, TA = 25 °C -1 VDD = 3.
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STM8L151x2, STM8L151x3 Electrical parameters Figure 18. Typical HSI frequency vs VDD 18.0 17.5 HSI frequency [MHz] 17.0 16.5 16.0 15.5 15.0 -40°C 25°C 90°C 130°C 14.5 14.0 13.5 13.0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] 3 3.15 3.3 3.45 3.6 Low speed internal RC oscillator (LSI) In the following table, data is based on characterization results, not tested in production. Table 30.
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Electrical parameters STM8L151x2, STM8L151x3 Figure 19. Typical LSI frequency vs. VDD 45 43 LSI frequency [kHz] 41 39 37 35 33 -40°C 25°C 90°C 130°C 31 29 27 25 1.6 2.1 2.6 VDD [V] 70/112 Doc ID 018780 Rev 4 3.1 3.
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STM8L151x2, STM8L151x3 7.3.5 Electrical parameters Memory characteristics TA = -40 to 125 °C unless otherwise specified. Table 31. RAM and hardware registers Symbol Parameter Conditions Min Typ VRM Data retention mode (1) Halt mode (or Reset) 1.65 Max Unit V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production. Flash memory Table 32.
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Electrical parameters 7.3.6 STM8L151x2, STM8L151x3 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
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STM8L151x2, STM8L151x3 Table 34.
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Electrical parameters STM8L151x2, STM8L151x3 Figure 20. Typical VIL and VIH vs VDD (high sink I/Os) 3 -40°C 25°C 90°C 130°C VIL and VIH [V] 2.5 2 1.5 1 0.5 0 1.6 2.1 2.6 VDD [V] 3.1 3.6 Figure 21. Typical VIL and VIH vs VDD (true open drain I/Os) 3 -40°C 25°C 90°C 130°C VIL and VIH [V] 2.5 2 1.5 1 0.5 0 1.6 74/112 2.1 2.6 VDD [V] Doc ID 018780 Rev 4 3.1 3.
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STM8L151x2, STM8L151x3 Electrical parameters Figure 22. Typical pull-up resistance RPU vs VDD with VIN=VSS 60 -40°C 25°C 90°C 130°C Pull-Up resistance [kΩ] 55 50 45 40 35 30 1.6 1.8 2 2.2 2.4 2.6 VDD [V] 2.8 3 3.2 3.4 3.6 Figure 23. Typical pull-up current Ipu vs VDD with VIN=VSS 120 Pull-Up current [μA] 100 80 -40°C 25°C 90°C 130°C 60 40 20 0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] Doc ID 018780 Rev 4 3 3.15 3.3 3.45 3.
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Electrical parameters STM8L151x2, STM8L151x3 Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 35. Output driving current (high sink ports) I/O Symbol Type Output low level voltage for an I/O pin High sink VOL (1) Parameter VOH (2) Output high level voltage for an I/O pin Conditions Min Max Unit IIO = +2 mA, VDD = 3.0 V 0.45 V IIO = +2 mA, VDD = 1.8 V 0.45 V IIO = +10 mA, VDD = 3.0 V 0.7 V IIO = -2 mA, VDD = 3.0 V VDD-0.
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STM8L151x2, STM8L151x3 Electrical parameters Figure 24. Typ. VOL @ VDD = 3.0 V (high sink ports) Figure 25. Typ. VOL @ VDD = 1.8 V (high sink ports) 1 0.7 -40°C 25°C 90°C 130°C 0.5 0.6 -40°C 25°C 90°C 130°C 0.5 VOL [V] VOL [V] 0.75 0.25 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 0 0 IOL [mA] 1 2 3 4 5 6 7 8 IOL [mA] ai18226 Figure 26. Typ. VOL @ VDD = 3.0 V (true open drain ports) ai18227 Figure 27. Typ. VOL @ VDD = 1.8 V (true open drain ports) 0.5 0.
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Electrical parameters STM8L151x2, STM8L151x3 NRST pin Subject to general operating conditions for VDD and TA unless otherwise specified. Table 38. NRST pin characteristics Symbol Parameter Conditions Min Max Typ VIL(NRST) NRST input low level voltage (1) VSS 0.8 VIH(NRST) NRST input high level voltage (1) 1.4 VDD NRST output low level voltage (1) VOL(NRST) IOL = 2 mA for 2.7 V ≤ VDD ≤ 3.6 V Unit V 0.4 IOL = 1.5 mA for VDD < 2.
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STM8L151x2, STM8L151x3 Electrical parameters Figure 31. Typical NRST pull-up current Ipu vs VDD 120 -40°C 25°C 90°C 130°C Pull-Up current [μA] 100 80 60 40 20 0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max. level specified in Table 38. Otherwise the reset is not taken into account internally.
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Electrical parameters 7.3.8 STM8L151x2, STM8L151x3 Communication interfaces SPI1 - Serial peripheral interface Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under ambient temperature, fSYSCLK frequency and VDD supply voltage conditions summarized in Section 7.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 39.
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STM8L151x2, STM8L151x3 Electrical parameters Figure 33. SPI1 timing diagram - slave mode and CPHA=0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134 Figure 34.
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Electrical parameters STM8L151x2, STM8L151x3 Figure 35. SPI1 timing diagram - master mode(1) High NSS input SCK output CPHA= 0 CPOL=0 SCK output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM8L151x2, STM8L151x3 Electrical parameters I2C - Inter IC control interface Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified. The STM8L I2C interface (I2C1) meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 40.
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Electrical parameters STM8L151x2, STM8L151x3 Figure 36. Typical application with I2C bus and timing diagram 1) VDD 4.7kΩ I2C VDD 4.7kΩ BUS 100Ω SDA 100Ω SCL STM8L REPEATED START START tsu(STA) tw(STO:STA) SDA tr(SDA) tf(SDA) tsu(SDA) th(SDA) tr(SCL) tf(SCL) STOP SCL th(STA) tw(SCLH) tw(SCLL) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.
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STM8L151x2, STM8L151x3 7.3.9 Electrical parameters Embedded reference voltage In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 41. Reference voltage characteristics Symbol IREFINT TS_VREFINT(1)(2) IBUF(2) VREFINT out ILPBUF(2) Parameter Conditions Min Internal reference voltage consumption Typ Max. 1.
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Electrical parameters 7.3.10 STM8L151x2, STM8L151x3 Temperature sensor In the following table, data is based on characterization results, not tested in production, unless otherwise specified. Table 42. TS characteristics Symbol Parameter Min Typ Max. Unit V90 (1) Sensor reference voltage at 90°C ±5 °C, 0.580 0.597 0.614 V ±1 ±2 °C 1.62 1.65 mV/°C 3.
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STM8L151x2, STM8L151x3 Electrical parameters In the following table, data is guaranteed by design, not tested in production. Table 44. Symbol VDDA Comparator 2 characteristics Parameter Conditions Min Typ Max(1) Unit Analog supply voltage 1.65 3.6 V TA Temperature range -40 125 °C VIN Comparator 2 input voltage range 0 VDDA V tSTART td slow td fast Fast mode 15 20 Slow mode 20 25 1.65 V ≤ VDDA ≤ 2.7 V 1.8 3.5 2.7 V ≤ VDDA ≤ 3.6 V 2.5 6 1.65 V ≤ VDDA ≤ 2.7 V 0.8 2 2.
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Electrical parameters 7.3.12 STM8L151x2, STM8L151x3 12-bit ADC1 characteristics In the following table, data is guaranteed by design, not tested in production. Table 45. Symbol ADC1 characteristics Parameter VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage IVDDA Current on the VDDA input pin IVREF+ Current on the VREF+ input pin Conditions 2.4 V ≤ VDDA≤ 3.6 V Min Max Unit 1.8 3.6 V 2.4 VDDA V 1.8 V ≤ VDDA≤ 2.
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STM8L151x2, STM8L151x3 Table 45. Symbol tS ADC1 characteristics (continued) Parameter Sampling time tconv 12-bit conversion time tWKUP Wakeup time from OFF state tIDLE(6) tVREFINT Electrical parameters Conditions Min VAIN on PF0 fast channel VDDA < 2.4 V 0.43(4)(5) µs VAIN on PF0 fast channel 2.4 V ≤ VDDA≤ 3.6 V 0.22(4)(5) µs VAIN on slow channels VDDA < 2.4 V 0.86(4)(5) µs VAIN on slow channels 2.4 V ≤ VDDA≤ 3.6 V 0.
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Electrical parameters STM8L151x2, STM8L151x3 In the following three tables, data is guaranteed by characterization result, not tested in production. Table 46. ADC1 accuracy with VDDA = 3.3 V to 2.5 V Symbol Parameter Conditions Typ Max 1 1.6 Differential non linearity fADC1 = 8 MHz 1 1.6 fADC1 = 4 MHz 1 1.5 fADC1 = 16 MHz 1.2 2 fADC1 = 8 MHz 1.2 1.8 fADC1 = 4 MHz 1.2 1.7 fADC1 = 16 MHz 2.2 3.0 fADC1 = 8 MHz 1.8 2.5 fADC1 = 4 MHz 1.8 2.3 fADC1 = 16 MHz 1.
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STM8L151x2, STM8L151x3 Electrical parameters Figure 37. ADC1 accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET 7 (1) 6 5 4 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one.
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Electrical parameters STM8L151x2, STM8L151x3 Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA) STM8L V REF+ External reference 1 μF // 10 nF Supply V DDA 1 μF // 10 nF V SSA/V REF- ai17031b Figure 40.
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STM8L151x2, STM8L151x3 Electrical parameters Figure 41. Max. dynamic current consumption on VREF+ supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700μA 300μA MS18181V1 Table 49. RAIN max for fADC = 16 MHz RAIN max (kohm) tS (cycles) tS (µs) Slow channels Fast channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 0.7 Not allowed 9 0.5625 0.8 Not allowed 2.0 1.
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Electrical parameters STM8L151x2, STM8L151x3 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
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STM8L151x2, STM8L151x3 Electrical parameters Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and charge device model. This test conforms to the JESD22-A114A/A115A standard. Table 52.
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Electrical parameters 7.4 STM8L151x2, STM8L151x3 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 14: General operating conditions on page 52.
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STM8L151x2, STM8L151x3 8 Option bytes Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated memory block. All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM address. See Table 55 for details on option byte addresses.
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Option bytes Table 56. STM8L151x2, STM8L151x3 Option byte description Option byte Option description No. OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Disable readout protection (write access via SWIM protocol) Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031). OPT1 UBC[7:0] Size of the user boot code area 0x00: UBC is not protected. 0x01: Page 0 is write protected. 0x02: Page 0 and 1 reserved for the UBC and write protected.
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STM8L151x2, STM8L151x3 Table 56. Option bytes Option byte description (continued) Option byte Option description No. OPT5 BOR_ON: 0: Brownout reset off 1: Brownout reset on BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 19 for details on the thresholds according to the value of BOR_TH bits. OPTBL OPTBL[15:0]: This option is checked by the boot ROM code after reset.
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Unique ID 9 STM8L151x2, STM8L151x3 Unique ID STM8 devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.
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STM8L151x2, STM8L151x3 Package characteristics 10 Package characteristics 10.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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Package characteristics STM8L151x2, STM8L151x3 10.2 Package mechanical data 10.2.1 48-pin low profile quad flat 7x7mm package (LQFP48) Figure 42. LQFP48 package outline D ccc $ D1 " " D3 25 36 24 37 L1 b E3 E1 E 48 Pin 1 identification 13 1 L A1 K D 12 5B_ME Table 58. LQFP48 package mechanical data inches(1) mm Dim. Min Typ A Max Min 1.6 A1 0.05 A2 1.35 b 0.17 c 0.09 D 8.8 D1 6.8 D3 Max 0.063 0.15 0.002 1.4 1.45 0.0531 0.0551 0.22 0.27 0.0067 0.0087 0.
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STM8L151x2, STM8L151x3 10.2.2 Package characteristics 32-lead ultra thin fine pitch quad flat no-lead 5x5 mm package (UFQFPN32) Figure 43. UFQFPN32 package outline Seating plane C ddd C A A1 A3 D e 16 9 17 8 E2 E b 24 1 L 32 Pin # 1 ID R = 0.30 D2 Bottom view L A0B8_ME 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package.
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Package characteristics Table 59. STM8L151x2, STM8L151x3 UFQFPN32 package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A 0.5 0.55 0.6 0.0197 0.0217 0.0236 A1 0.00 0.02 0.05 0 0.0008 0.0020 A3 0.152 0.006 b 0.18 0.23 0.28 0.0071 0.0091 0.0110 D 4.90 5.00 5.10 0.1929 0.1969 0.2008 D2 3.50 0.1378 E 4.90 5.00 5.10 0.1929 0.1969 0.2008 E2 3.40 3.50 3.60 0.1339 0.1378 0.1417 e 0.500 L 0.30 ddd 0.40 0.0197 0.50 0.0118 0.08 0.0157 0.
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STM8L151x2, STM8L151x3 10.2.3 Package characteristics 28-lead ultra thin fine pitch quad flat no-lead 4x4 mm package (UFQFPN28) Figure 45. UFQFPN28 package outline D B D1 A Seating Plane Co 130x45° Pin 1 corner E1 E L1 1 L Pin 1 ID 28 Detail Z Detail Z Ro.125 Typ. e T A1 A Seating Plane b A0B0_ME_V4 1. Drawing is not to scale. Table 60. UFQFPN28 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 -0.
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Package characteristics STM8L151x2, STM8L151x3 Figure 46. Recommended UFQFPN28 footprint (dimensions in mm) 3.30 0.50 3.20 3.20 4.30 3.30 0.30 0.50 0.55 0.50 1. Drawing is not to scale.
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STM8L151x2, STM8L151x3 10.2.4 Package characteristics 20-lead ultra thin fine pitch quad flat no-lead package (UFQFPN20) Figure 47. UFQFPN20 - 20-lead ultra thin fine pitch quad flat package outline (3x3) D E Pin 1 TOP VIEW L1 D ddd L4 e 10 A3 L2 5 11 e b E 1 15 20 16 L3 A1 BOTTOM VIEW A SIDE VIEW A0A5_ME_V2 Figure 48. UFQFPN20 recommended footprint (dimensions in mm) A0A5_FP_V2 1. Drawing is not to scale.
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Package characteristics Table 61. STM8L151x2, STM8L151x3 UFQFPN20 - 20-lead ultra thin fine pitch quad flat package (3x3) package mechanical data inches(1) mm Dim. Min Typ Max Min Typ D 3.000 0.1181 E 3.000 0.1181 Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 A3 θ 0.152 0.0060 0° e 12 ° 0° 0.500 12 ° 0.0197 L1 0.500 0.550 0.600 0.0197 0.0217 0.0236 L2 0.300 0.350 0.400 0.0118 0.0138 0.0157 L3 0.150 0.0059 L4 0.
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STM8L151x2, STM8L151x3 Package characteristics Figure 49. TSSOP20 - 20-pin thin shrink small outline package D 20 11 c E1 1 E 10 k aaa CP A1 A L A2 L1 b e YA_ME Table 62. TSSOP20 - 20-pin thin shrink small outline package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A — — 1.200 — — 0.0472 A1 0.050 — 0.150 0.0020 — 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 — 0.300 0.0075 — 0.0118 c 0.090 — 0.200 0.0035 — 0.0079 D 6.400 6.
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Device ordering information 11 STM8L151x2, STM8L151x3 Device ordering information Figure 50.
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STM8L151x2, STM8L151x3 12 Revision history Revision history Table 63. Document revision history Date Revision 08-Jun-2011 1 Initial release 2 Modified Figure 8: Memory map on page 33.
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STM8L151x2, STM8L151x3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.