Datasheet

Electrical parameters STM8L15xx8, STM8L15xR6
88/134 DocID17943 Rev 6
9.3.4 Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for V
DD
and T
A
.
5. Data based on a differential I
DD
measurement between DAC in reset configuration and continuous DAC conversion of
V
DD
/2. Floating DAC output.
6. Data based on a differential I
DD
measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
enabled with static inputs. Supply current of internal reference voltage excluded.
7. Including supply current of internal reference voltage.
Table 28. Current consumption under external reset
Symbol Parameter Conditions Typ. Unit
I
DD(RST)
Supply current under
external reset
(1)
PB1/PB3/PA5 pins are
externally tied to V
DD
V
DD
= 1.8 V 48
µAV
DD
= 3 V 80
V
DD
= 3.6 V 95
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.
Table 29. HSE external clock characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
f
HSE_ext
(1)
1. Guaranteed by design, not tested in production.
External clock source
frequency
116MHz
V
HSEH
OSC_IN input pin high level
voltage
0.7 x V
DD
V
DD
V
V
HSEL
OSC_IN input pin low level
voltage
V
SS
0.3 x V
DD
C
in(HSE)
(1)
OSC_IN input capacitance 2.6 pF
I
LEAK_HSE
OSC_IN input leakage
current
V
SS
< V
IN
< V
DD
±1 µA