Datasheet

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STM8L15xx8, STM8L15xR6 Memory and register map
61
0x00 5386 to
0x00 5387
Reserved area (2 bytes)
0x00 5388
DAC
DAC_CH1RDHRH
DAC channel 1 right aligned data holding
register high
0x00
0x00 5389
DAC_CH1RDHRL
DAC channel 1 right aligned data holding
register low
0x00
0x00 538A to
0x00 538B
Reserved area (2 bytes)
0x00 538C DAC
DAC_CH1LDHRH
DAC channel 1 left aligned data holding
register high
0x00
0x00 538D DAC
DAC_CH1LDHRL
DAC channel 1 left aligned data holding
register low
0x00
0x00 538E
to 0x00 538F
Reserved area (2 bytes)
0x00 5390 DAC
DAC_CH1DHR8
DAC channel 1 8-bit data holding register 0x00
0x00 5391 to
0x00 5393
Reserved area (3 bytes)
0x00 5394
DAC
DAC_CH2RDHRH
DAC channel 2 right aligned data holding
register high
0x00
0x00 5395
DAC_CH2RDHRL
DAC channel 2 right aligned data holding
register low
0x00
0x00 5396 to
0x00 5397
Reserved area (2 bytes)
0x00 5398
DAC
DAC_CH2LDHRH
DAC channel 2 left aligned data holding
register high
0x00
0x00 5399
DAC_CH2LDHRL
DAC channel 2 left aligned data holding
register low
0x00
0x00 539A
to 0x00 539B
Reserved area (2 bytes)
0x00 539C DAC
DAC_CH2DHR8
DAC channel 2 8-bit data holding register 0x00
0x00 539D
to 0x00 539F
Reserved area (3 bytes)
0x00 53A0
DAC
DAC_DCH1RDHRH
DAC channel 1 right aligned data holding
register high
0x00
0x00 53A1
DAC_DCH1RDHRL
DAC channel 1 right aligned data holding
register low
0x00
0x00 53A2
to 0x00 53AB
Reserved area (3 bytes)
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status