Datasheet

Memory and register map STM8L15xx8, STM8L15xR6
52/134 DocID17943 Rev 6
0x00 5310
TIM5
TIM5_ARRL TIM5 Auto-reload register low 0xFF
0x00 5311 TIM5_CCR1H TIM5 Capture/Compare register 1 high 0x00
0x00 5312 TIM5_CCR1L TIM5 Capture/Compare register 1 low 0x00
0x00 5313 TIM5_CCR2H TIM5 Capture/Compare register 2 high 0x00
0x00 5314 TIM5_CCR2L TIM5 Capture/Compare register 2 low 0x00
0x00 5315 TIM5_BKR TIM5 break register 0x00
0x00 5316 TIM5_OISR TIM5 output idle state register 0x00
0x00 5317
to
0x00 533F
Reserved area
0x00 5340
ADC1
ADC1_CR1 ADC1 configuration register 1 0x00
0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00
0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F
0x00 5343 ADC1_SR ADC1 status register 0x00
0x00 5344 ADC1_DRH ADC1 data register high 0x00
0x00 5345 ADC1_DRL ADC1 data register low 0x00
0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F
0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF
0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00
0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00
0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00
0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00
0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00
0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00
0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00
0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00
0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00
0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00
0x00 5352 to
0x00 537F
Reserved area (46 bytes)
0x00 5380
DAC
DAC_CH1CR1
DAC channel 1 control register 1 0x00
0x00 5381
DAC_CH1CR2
DAC channel 1 control register 2 0x00
0x00 5382
DAC_CH2CR1
DAC channel 2 control register 1 0x00
0x00 5383
DAC_CH2CR2
DAC channel 2 control register 2 0x00
0x00 5384
DAC_SWTRIG
DAC software trigger register 0x00
0x00 5385
DAC_SR
DAC status register 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status