Datasheet

DocID17943 Rev 6 51/134
STM8L15xx8, STM8L15xR6 Memory and register map
61
0x00 52D2
TIM1
TIM1_DCR2 TIM1 DMA1 control register 2 0x00
0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00
0x00 52D4
to
0x00 52DF
Reserved area (12 bytes)
0x00 52E0
TIM4
TIM4_CR1 TIM4 control register 1 0x00
0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00
0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00
0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00
0x00 52E4 TIM4_IER TIM4 Interrupt enable register 0x00
0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00
0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00
0x00 52E7 TIM4_CNTR TIM4 counter 0x00
0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00
0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00
0x00 52EA
to
0x00 52FE
Reserved area (21 bytes)
0x00 52FF IRTIM IR_CR Infrared control register 0x00
0x00 5300
TIM5
TIM5_CR1 TIM5 control register 1 0x00
0x00 5301 TIM5_CR2 TIM5 control register 2 0x00
0x00 5302 TIM5_SMCR TIM5 Slave mode control register 0x00
0x00 5303 TIM5_ETR TIM5 external trigger register 0x00
0x00 5304 TIM5_DER TIM5 DMA1 request enable register 0x00
0x00 5305 TIM5_IER TIM5 interrupt enable register 0x00
0x00 5306 TIM5_SR1 TIM5 status register 1 0x00
0x00 5307 TIM5_SR2 TIM5 status register 2 0x00
0x00 5308 TIM5_EGR TIM5 event generation register 0x00
0x00 5309 TIM5_CCMR1 TIM5 Capture/Compare mode register 1 0x00
0x00 530A TIM5_CCMR2 TIM5 Capture/Compare mode register 2 0x00
0x00 530B TIM5_CCER1 TIM5 Capture/Compare enable register 1 0x00
0x00 530C TIM5_CNTRH TIM5 counter high 0x00
0x00 530D TIM5_CNTRL TIM5 counter low 0x00
0x00 530E TIM5_PSCR TIM5 prescaler register 0x00
0x00 530F TIM5_ARRH TIM5 Auto-reload register high 0xFF
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status