Datasheet

Memory and register map STM8L15xx8, STM8L15xR6
48/134 DocID17943 Rev 6
0x00 521F
to
0x00 522F
Reserved area (17 bytes)
0x00 5230
USART1
USART1_SR USART1 status register 0xC0
0x00 5231 USART1_DR USART1 data register 0xXX
0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00
0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00
0x00 5234 USART1_CR1 USART1 control register 1 0x00
0x00 5235 USART1_CR2 USART1 control register 2 0x00
0x00 5236 USART1_CR3 USART1 control register 3 0x00
0x00 5237 USART1_CR4 USART1 control register 4 0x00
0x00 5238 USART1_CR5 USART1 control register 5 0x00
0x00 5239 USART1_GTR USART1 guard time register 0x00
0x00 523A USART1_PSCR USART1 prescaler register 0x00
0x00 523B
to
0x00 524F
Reserved area (21 bytes)
0x00 5250
TIM2
TIM2_CR1 TIM2 control register 1 0x00
0x00 5251 TIM2_CR2 TIM2 control register 2 0x00
0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00
0x00 5253 TIM2_ETR TIM2 external trigger register 0x00
0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00
0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00
0x00 5256 TIM2_SR1 TIM2 status register 1 0x00
0x00 5257 TIM2_SR2 TIM2 status register 2 0x00
0x00 5258 TIM2_EGR TIM2 event generation register 0x00
0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00
0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00
0x00 525B TIM2_CCER1 TIM2 capture/compare enable register 1 0x00
0x00 525C TIM2_CNTRH TIM2 counter high 0x00
0x00 525D TIM2_CNTRL TIM2 counter low 0x00
0x00 525E TIM2_PSCR TIM2 prescaler register 0x00
0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF
0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF
0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status