Datasheet

DocID17943 Rev 6 39/134
STM8L15xx8, STM8L15xR6 Memory and register map
61
5 Memory and register map
5.1 Memory mapping
The memory map is shown in Figure 9.
Figure 9. Memory map
1. Refer to Table 9 for an overview of hardware register mapping, to Table 8 for details on I/O port hardware
registers, and to Table 10 for information on CPU/SWIM/debug module controller registers.
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INCLUDING
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