Datasheet

DocID17943 Rev 6 19/134
STM8L15xx8, STM8L15xR6 Functional overview
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3.6 LCD (Liquid crystal display)
The LCD is only available on STM8L152xx devices.
The liquid crystal display drives up to 8 common terminals and up to 40 segment terminals
to drive up to 320 pixels. It can also be configured to drive up to 4 common and 44
segments (up to 176 pixels).
• Internal step-up converter to guarantee contrast control whatever V
DD
.
• Static 1/2, 1/3, 1/4, 1/8 duty supported.
• Static 1/2, 1/3, 1/4 bias supported.
• Phase inversion to reduce power consumption and EMI.
• Up to 8 pixels which can programmed to blink.
• The LCD controller can operate in Halt mode.
Note: Unnecessary segments and common pins can be used as general I/O pins.
3.7 Memories
The high density and medium+ density STM8L15xx devices have the following main
features:
• Up to 4 Kbytes of RAM
• The non-volatile memory is divided into three arrays:
– Up to 64 Kbytes of medium-density embedded Flash program memory
– Up to 2 Kbytes of Data EEPROM
– Option bytes.
The EEPROM embeds the error correction code (ECC) feature. It supports the read-while-
write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.
3.8 DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, DAC1,DAC2, I2C1, SPI1, SPI2, USART1,
USART2, USART3, and the 5 Timers.