Datasheet

DocID17943 Rev 6 117/134
STM8L15xx8, STM8L15xR6 Electrical parameters
121
Figure 44. Maximum dynamic current consumption on V
REF+
supply pin during ADC
conversion
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 45 or Figure 46,
depending on whether V
REF+
is connected to V
DDA
or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.
ADC clock
Sampling (n cycles)
Conversion (12 cycles)
I
ref+
300μA
700μA
MS32625V1
Table 57. R
AIN
max for f
ADC
= 16 MHz
(1)
Ts
(cycles)
Ts
(µs)
R
AIN
max (kohm)
Slow channels Fast channels
2.4 V < V
DDA
< 3.6 V 1.8 V < V
DDA
< 2.4 V 2.4 V < V
DDA
< 3.3 V 1.8 V < V
DDA
< 2.4 V
4 0.25 Not allowed Not allowed 0.7 Not allowed
9 0.5625 0.8 Not allowed 2.0 1.0
16 1 2.0 0.8 4.0 3.0
24 1.5 3.0 1.8 6.0 4.5
48 3 6.8 4.0 15.0 10.0
96 6 15.0 10.0 30.0 20.0
192 12 32.0 25.0 50.0 40.0
384 24 50.0 50.0 50.0 50.0
1. Guaranteed by design, not tested in production.