Datasheet

DocID17943 Rev 6 101/134
STM8L15xx8, STM8L15xR6 Electrical parameters
121
Figure 35. Typical NRST pull-up resistance R
PU
vs. V
DD
Figure 36. Typical NRST pull-up current I
pu
vs. V
DD
The reset network shown in Figure 37 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the V
IL
max. level specified in
Table 4 2. Otherwise the reset is not taken into account internally. For power consumption-
sensitive applications, the capacity of the external reset capacitor can be reduced to limit the
charge/discharge current. If the NRST signal is used to reset the external circuitry, the user
must pay attention to the charge/discharge time of the external capacitor to meet the reset
timing conditions of the external devices. The minimum recommended capacity is 10 nF.
Figure 37. Recommended NRST pin configuration







          
6
$$
;6=
0ULLUPRESISTANCE;K
7
=
#
#
#
#
AI
AI







             
6
$$
;6=
0ULL5
PCURRENT;!=
#
#
#
#
0.1MF
EXTERNAL
RESET
CIRCUIT
STM8L
&ILTER
2
05
6
$$
).4%2.!,2%3%4
RSTIN
MS32619V1