Datasheet

Functional overview STM8L052R8
16/55 Doc ID 023133 Rev 2
3.6 LCD (Liquid crystal display)
The LCD is only available on STM8L052xx devices.
The liquid crystal display drives up to 8 common terminals and up to 24 segment terminals
to drive up to 192 pixels. It can also be configured to drive up to 4 common and 28 segments
(up to 112 pixels).
● Internal step-up converter to guarantee contrast control whatever V
DD
.
● Static 1/2, 1/3, 1/4, 1/8 duty supported.
● Static 1/2, 1/3, 1/4 bias supported.
● Phase inversion to reduce power consumption and EMI.
● Up to 8 pixels which can be programmed to blink.
● The LCD controller can operate in Halt mode.
Note: Unnecessary segments and common pins can be used as general I/O pins.
3.7 Memories
The high density value line STM8L05xxx devices have the following main features:
● 4 Kbytes of RAM
● The non-volatile memory is divided into three arrays:
– 64 Kbytes of high density embedded Flash program memory
– 256 bytes of data EEPROM
–Option bytes
The EEPROM embeds the error correction code (ECC) feature. It supports the read-while-
write (RWW): it is possible to execute the code from the program matrix while
programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.
3.8 DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, I2C1, SPI1, SPI 2, USART1, USART2, USART3
and the five timers.