Datasheet

Interrupt vector mapping STM8L052C6
46/52 Doc ID 022924 Rev 2
19 TIM2
TIM2 update/overflow/
trigger/break
interrupt
- - Yes Yes 0x00 8054
20 TIM2
TIM2capture/
compare interrupt
- - Yes Yes 0x00 8058
21 TIM3
TIM3 update/overflow/
trigger/break interrupt
- - Yes Yes 0x00 805C
22 TIM3
TIM3 capture/compare
interrupt
- - Yes Yes 0x00 8060
23 TIM1
Update /overflow/trigger/
COM
- - - Yes 0x00 8064
24 TIM1 Capture/compare - - - Yes 0x00 8068
25 TIM4
TIM4 update/overflow/
trigger interrupt
- - Yes Yes 0x00 806C
26 SPI1
SPI1 TX buffer empty/
RX buffer not empty/
error/wakeup interrupt
Yes Yes Yes Yes 0x00 8070
27 USART1
USART1transmit data
register empty/
transmission complete
interrupt
- - Yes Yes 0x00 8074
28 USART1
USART1 received data
ready/overrun error/
idle line detected/parity
error/global error interrupt
- - Yes Yes 0x00 8078
29 I
2
C1 I
2
C1 interrupt
(3)
Yes Yes Yes Yes 0x00 807C
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode. In WFE mode, the
interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode.
When the interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
2. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt (see External interrupt port select register (EXTI_CONF) in the RM0031).
3. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
Table 9. Interrupt mapping (continued)
IRQ
No.
Source
block
Description
Wakeup
from Halt
mode
Wakeup
from
Active-
halt mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)
(1)
Vector
address